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參數(shù)資料
| 型號： | AD7711 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS Signal Conditioning ADC with RTD Excitation Currents(RTD激勵電流LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
| 中文描述： | LC2MOS信號調(diào)理模數(shù)轉(zhuǎn)換器（RTD的激勵電流LC2MOS信號調(diào)節(jié)的A / D轉(zhuǎn)換器與RTD激勵電流） |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 256K |
| 代理商： | AD7711 |
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REV. F
–16–
AD7711
on the AIN1(+) input is +1.25 V to +3.75 V. If AIN1(–) is
+1.25 V and the AD7711 is configured for bipolar mode with a
gain of 1 and a V
REF
of +2.5 V, the analog input range on the
AIN1(+) input is –1.25 V to +3.75 V. For the AIN2 input, the
input signals are referenced to AGND.
REFERENCE INPUT/OUTPUT
The AD7711 contains a temperature compensated +2.5 V refer-
ence which has an initial tolerance of
±
1%. This reference volt-
age is provided at the REF OUT pin and it can be used as the
reference voltage for the part by connecting the REF OUT pin
to the REF IN(+) pin. This REF OUT pin is a single-ended
output, referenced to AGND, which is capable of providing up
to 1 mA to an external load. In applications where REF OUT is
connected directly to REF IN(+), REF IN(–) should be tied to
AGND to provide the nominal +2.5 V reference for the
AD7711.
The reference inputs of the AD7711, REF IN(+) and
REF IN(–), provide a differential reference input capability. The
common-mode range for these differential inputs is from V
SS
to
AV
DD
. The nominal differential voltage, V
REF
(REF IN(+) –
REF IN(–)), is +2.5 V for specified operation, but the reference
voltage can go to +5 V with no degradation in performance
provided that the absolute value of REF IN(+) and REF IN(–)
does not exceed its AV
DD
and V
SS
limits and the V
BIAS
input
voltage range limits are obeyed. The part is also functional with
V
REF
voltages down to 1 V but with degraded performance as
the output noise will, in terms of LSB size, be larger. REF
IN(+) must always be greater than REF IN(–) for correct opera-
tion of the AD7711.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs. The maximum dc input leakage
current is 10 pA (
±
1 nA over temperature) and source resis-
tance may result in gain errors on the part. The reference inputs
look like the analog input (see Figure 7). In this case, R
INT
is
5 k
typ and C
INT
varies with gain. The input sample rate is
f
CLK IN
/256 and does not vary with gain. For gains of 1 to 8 C
INT
is 20 pF; for a gain of 16 it is 10 pF; for a gain of 32 it is 5 pF;
for a gain of 64 it is 2.5 pF; and for a gain of 128 it is 1.25 pF.
The digital filter of the AD7711 removes noise from the refer-
ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor-
mance outlined in Tables I and II assumes a clean reference. If
the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7711. Using the on-chip
reference as the reference source for the part (i.e., connecting
REF OUT to REF IN) results in somewhat degraded output
noise performance from the AD7711 for portions of the noise
table that are dominated by the device noise. The on-chip
reference noise effect is eliminated in ratiometric applications
where the reference is used to provide the excitation voltage for
the analog front end. The connection shown in Figure 8 is rec-
ommended when using the on-chip reference. Recommended
reference voltage sources for the AD7711 include the AD580
and AD680 2.5 V references.
AD7711
REF OUT
REF IN(+)
REF IN(–)
Figure 8. REF OUT/REF IN Connection
V
BIAS
Input
The V
BIAS
input determine at what voltage the internal analog
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator and, as such, it should
be driven from a low impedance point to minimize errors.
For maximum internal headroom, the V
BIAS
voltage should be
set halfway between AV
DD
and V
SS
. The difference between
AV
DD
and (V
BIAS
+ 0.85
×
V
REF
) determines the amount of
headroom the circuit has at the upper end, while the difference
between V
SS
and (V
BIAS
– 0.85
×
V
REF
) determines the amount
of headroom the circuit has at the lower end. Care should be
taken in choosing a V
BIAS
voltage to ensure that it stays within
prescribed limits. For single +5 V operation, the selected V
BIAS
voltage must ensure that V
BIAS
±
0.85
×
V
REF
does not exceed
AV
DD
or V
SS
or that the V
BIAS
voltage itself is greater than V
SS
+ 2.1 V and less than AV
DD
– 2.1 V. For single +10 V operation
or dual
±
5 V operation, the selected V
BIAS
voltage must ensure
that V
BIAS
×
0.85
×
V
REF
does not exceed AV
DD
or V
SS
or that
the V
BIAS
voltage itself is greater than V
SS
+ 3 V or less than
AV
DD
– 3 V. For example, with AV
DD
= +4.75 V, V
SS
= 0 V
and V
REF
= +2.5 V, the allowable range for the V
BIAS
voltage is
+2.125 V to +2.625 V. With AV
DD
= +9.5 V, V
SS
= 0 V and
V
REF
= +5 V, the range for V
BIAS
is +4.25 V to +5.25 V. With
AV
DD
= +4.75 V, V
SS
= –4.75 V and V
REF
= +2.5 V, the V
BIAS
range is –2.625 V to +2.625 V.
The V
BIAS
voltage does have an effect on the AV
DD
power sup-
ply rejection performance of the AD7711. If the V
BIAS
voltage
tracks the AV
DD
supply, it improves the power supply rejection
from the AV
DD
supply line from 80 dB to 95 dB. Using an
external Zener diode, connected between the AV
DD
line and
V
BIAS
, as the source for the V
BIAS
voltage gives the improvement
in AV
DD
power supply rejection performance.
USING THE AD7711
SYSTEM DESIGN CONSIDERATIONS
The AD7711 operates differently from successive approxima-
tion ADCs or integrating ADCs. Since it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter and the output can be
read at any time, either synchronously or asynchronously.
Clocking
The AD7711 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be con-
nected between MCLK IN and MCLK OUT, in which case the
clock circuit will function as a crystal controlled oscillator. For
lower clock frequencies, a ceramic resonator may be used
instead of the crystal. For these lower frequency oscillators,
external capacitors may be required on either the ceramic reso-
nator or on the crystal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7711A | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Signal Conditioning ADC with RTD Current Source |
| AD7711AAN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 24-Bit |
| AD7711AAR | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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