參數(shù)資料
型號： AD7710*
廠商： Analog Devices, Inc.
英文描述： Signal Conditioning ADC
中文描述： ADC的信號調(diào)理
文件頁數(shù)： 6/28頁
文件大?。?/td> 220K
REV. F
–6–
AD7710
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
Units
Conditions/Comments
External Clocking Mode
f
SCLK
t
20
t
21
t
22
t
t
23
t
257
f
CLK IN
/5
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
10
2
×
t
CLK IN
+ 20
2
×
t
CLK IN
2
×
t
CLK IN
t
CLK IN
+ 10
10
t
CLK IN
+ 10
10
5
×
t
CLK IN
/2 + 50
0
0
4
×
t
CLK IN
2
×
t
CLK IN
– SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
Data Access Time (
RFS
Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
t
26
t
27
t
t
28
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Falling Edge to
DRDY
High
SCLK to Data Valid Hold Time
t
t
30
t
32
t
33
t
34
t
35
t
36
RFS
/
TFS
to SCLK Falling Edge Hold Time
RFS
to Data Valid Hold Time
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
SCLK Falling Edge to
TFS
Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
The AD7710 is specified with a 10 MHz clock for AV
DD
voltages of +5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7710 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5
The AD7710 is production tested with f
at 10 MHz (8 MHz for AV
DD
> +5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
8
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
PIN CONFIGURATION
DIP AND SOIC
SCLK
MCLK IN
DGND
DV
DD
MODE
AIN1(+)
AGND
MCLK OUT
A0
SDATA
AIN1(–)
I
OUT
REF OUT
REF IN(+)
REF IN(–)
AV
DD
V
BIAS
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
12
13
AD7710
SYNC
V
SS
DRDY
RFS
TFS
AIN2(+)
AIN2(–)
TO OUTPUT
PIN
+2.1V
1.6mA
200
m
A
100pF
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
相關(guān)PDF資料
PDF描述
AD7710 Signal Conditioning ADC(LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器)
AD7711AAR LC2MOS Signal Conditioning ADC with RTD Current Source
AD7711ASQ LC2MOS Signal Conditioning ADC with RTD Current Source
AD7711A* LC2MOS Signal Conditioning ADC with RTD Current Source
AD7711AN LC2MOS Signal Conditioning ADC with RTD Excitation Currents
相關(guān)代理商/技術(shù)參數(shù)
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AD7710AQ 功能描述:IC ADC 24BIT DIFF INP 24-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
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