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| 型號： | AD7710* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Signal Conditioning ADC |
| 中文描述： | ADC的信號調(diào)理 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 220K |
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AD7710
REV. F
–25–
REVERSE
ORDER OF
BITS
x3
START
WRITE DATA FROM
ACCUMULATOR TO
SERIAL BUFFER
BRING
TFS & A0 LOW
LOAD DATA FROM
ADDRESS TO
ACCUMULATOR
CONFIGURE &
INITIALIZE
m
C/
m
P
SERIAL PORT
BRING
RFS, TFS & A0 HIGH
BRING
TFS & A0 HIGH
END
Figure 16. Flowchart for Single Write Operation to the
AD7710
AD7710 to 8XC51 Interface
Figure 17 shows an interface between the AD7710 and the
8XC51 microcontroller. The AD7710 is configured for its exter-
nal clocking mode while the 8XC51 is configured in its Mode 0
serial interface mode. The
DRDY
line from the AD7710 is
connected to the Port P1.2 input of the 8XC51 so the
DRDY
line is polled by the 8XC51. The
DRDY
line can be connected
to the
INT1
input of the 8XC51 if an interrupt driven system is
preferred.
P1.0
P3.0
P3.1
P1.1
P1.2
P1.3
8XC51
AD7710
SDATA
A0
RFS
TFS
MODE
DRDY
SYNC
SCLK
DV
DD
Figure 17. AD7710 to 8XC51 Interface
Table VII shows some typical 8XC51 code used for a single 24-
bit read from the output register of the AD7710. Table VIII
shows some typical code for a single write operation to the con-
trol register of the AD7710. The 8XC51 outputs the LSB first
in a write operation while the AD7710 expects the MSB first so
the data to be transmitted has to be rearranged before being
written to the output serial register. Similarly, the AD7710
outputs the MSB first during a read operation while the 8XC51
expects the LSB first. Therefore, the data which is read into the
serial buffer needs to be rearranged before the correct data word
from the AD7710 is available in the accumulator.
Table VII. 8XC51 Code for Reading from the AD7710
MOV SCON,#00010001B;
Configure 8051 for MODE 0
Operation
Disable All Interrupts
Set P1.0, Used as
RFS
Set P1.1, Used as
TFS
Set P1.3, Used as A0
Sets Number of Bytes to Be Read in
A Read Operation
Start Address for Where Bytes Will
Be Loaded
Use P1.2 as
DRDY
MOV IE,#00010000B;
SETB 90H;
SETB 91H;
SETB 93H;
MOV R1,#003H;
MOV R0,#030H;
MOV R6,#004H;
WAIT:
NOP;
MOV A,P1;
ANL A,R6;
JZ READ;
SJMP WAIT;
READ:
CLR 90H;
CLR 98H;
POLL:
JB 98H, READ1
SJMP POLL
READ 1:
MOV A,SBUF;
RLC A;
MOV B.0,C;
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A;
INC R0;
DEC R1
MOV A,R1
JZ END
JMP WAIT
END:
SETB 90H
FIN:
SJMP FIN
Read Port 1
Mask Out All Bits Except
DRDY
If Zero Read
Otherwise Keep Polling
Bring
RFS
Low
Clear Receive Flag
Tests Receive Interrupt Flag
Read Buffer
Rearrange Data
Reverse Order of Bits
Write Data to Memory
Increment Memory Location
Decrement Byte Counter
Jump if Zero
Fetch Next Byte
Bring
RFS
High
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