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參數(shù)資料
| 型號： | AD7691BRMZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | LEAD FREE, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 682K |
| 代理商： | AD7691BRMZ |
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AD7691
4-Wire CS Mode Without Busy Indicator
This mode is usually used when multiple AD7691s are
connected to an SPI-compatible digital host.
Rev. 0 | Page 20 of 28
A connection diagram example using two AD7691s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7691 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
18
th
SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7691
can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7691
AD7691
0
Figure 38. 4-Wire CS Mode Without Busy Indicator Connection Diagram
SDO
D17
D16
D15
D1
D0
t
DIS
SCK
1
2
3
34
35
36
t
HSDO
t
DSDO
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI (CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
16
17
t
SCK
t
SCKL
t
SCKH
D0
D17
D16
19
20
18
SDI (CS2)
0
Figure 39. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
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