參數(shù)資料
型號(hào)： AD7691BRMZ-RL7
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN
中文描述： 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝： LEAD FREE, MO-187BA, MSOP-10
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 682K
代理商： AD7691BRMZ-RL7
AD7691
3-Wire CS Mode with Busy Indicator
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.
Rev. 0 | Page 19 of 28
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7691 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19
th
SCK falling edge,
or when CNV goes high, whichever is earlier, SDO returns to
high impedance.
If multiple AD7691s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
47k
CNV
SCK
SDO
SDI
VIO
AD7691
0
Figure 36. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
SDO
D17
D16
D1
D0
t
DIS
SCK
1
2
3
17
18
19
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
0
Figure 37. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
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