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| 型號(hào)： | AD7691BRMZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | LEAD FREE, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大小： | 682K |
| 代理商： | AD7691BRMZ-RL7 |
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AD7691
3-Wire CS Mode Without Busy Indicator
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
Rev. 0 | Page 18 of 28
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers, but CNV must be returned
high before the minimum conversion time elapses and then
held high for the maximum possible conversion time to avoid
the generation of the busy signal indicator. When the
conversion is complete, the AD7691 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge can allow a faster
reading rate, provided it has an acceptable hold time. After the
18
th
SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7691
0
Figure 34. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDO
D17
D16
D15
D1
D0
t
DIS
SCK
1
2
3
16
17
18
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
0
Figure 35. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
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