參數(shù)資料
型號： AD7686CRMZRL7
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 500KSPS 10MSOP
標(biāo)準(zhǔn)包裝： 1,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個偽差分，單極
配用： EVAL-AD7686CBZ-ND - BOARD EVALUATION FOR AD7686
AD7686
Rev. B | Page 21 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
029
69
-04
2
CNV
SCK
SDO
SDI
AD7686
B
CNV
SCK
SDO
SDI
AD7686
A
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
303132
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1DB0DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
02
96
9-
0
43
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
相關(guān)PDF資料
PDF描述
C091 31D105 100 2 CONN FEMALE 5POS CABLE STRGHT
MS27473E20B41P CONN PLUG 41POS STRAIGHT W/PINS
VI-2NH-CU-F2 CONVERTER MOD DC/DC 52V 200W
VE-25K-IU-F2 CONVERTER MOD DC/DC 40V 200W
GTC030-28-11P CONN RCPT 22POS PANEL MNT W/PINS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7686CRMZRL71 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN
AD7686XRM-U4 制造商:Analog Devices 功能描述:500 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC/CSP - Rail/Tube
AD7686XRM-U5 制造商:Analog Devices 功能描述:500 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC/CSP - Bulk
AD7687 制造商:AD 制造商全稱:Analog Devices 功能描述:3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23
AD76871 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*