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參數(shù)資料
| 型號： | AD7685BRMZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT PSEUDO-DIFF 10-MSOP |
| 產品培訓模塊： | Power Line Monitoring Motor Control |
| 設計資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標準包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 15mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | EVAL-AD7685CBZ-ND - BOARD EVAL FOR AD7685 |
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AD7685
Rev. C | Page 22 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7685s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7685s is shown in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the
chain mode. In this mode, CNV is held high during the
conversion phase and the subsequent data readback. When the
conversion is complete, the MSB is output onto SDO and the
AD7685 enters the acquisition phase and powers down. The
remaining data bits stored in the internal shift register are then
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 16 × N clocks are required to readback the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate and, consequently,
more AD7685s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time. For instance, with a 5 ns
digital host setup time and 3 V interface, up to eight AD7685s
running at a conversion rate of 220 kSPS can be daisy-chained
on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
02
96
8-
0
40
CNV
SCK
SDO
SDI
AD7685
B
CNV
SCK
SDO
SDI
AD7685
A
Figure 42. Chain Mode Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
303132
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1DB0DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
02
96
8-
0
41
Figure 43. Chain Mode Serial Interface Timing
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