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參數(shù)資料
| 型號： | AD7685BRMZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT PSEUDO-DIFF 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring Motor Control |
| 設(shè)計資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 15mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | EVAL-AD7685CBZ-ND - BOARD EVAL FOR AD7685 |
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AD7685
Rev. C | Page 20 of 28
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7685s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7685s is shown in
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7685 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input, which consequently outputs the
MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7685
can be read.
If multiple AD7685s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
02
96
8-
0
3
6
CNV
SCK
SDO
SDI
AD7685
CNV
SCK
SDO
SDI
AD7685
Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
tDIS
SCK
12
3
30
31
32
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14
15
tSCK
tSCKL
tSCKH
D0
D15
D14
17
18
16
SDI(CS2)
02
96
8-
03
7
Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
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