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參數(shù)資料
| 型號： | AD7667ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT UNIPOLAR 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 145mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個偽差分，單極 |
| 配用： | EVAL-AD7667CBZ-ND - BOARD EVALUATION FOR AD7667 |
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AD7667
Rev. 0 | Page 21 of 28
CONVERSION CONTROL
Figure 33 shows the detailed timing diagrams of the conversion
process. The AD7667 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD.
In Impulse mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7667 controls
the acquisition phase and automatically initiates a new con-
version. By keeping CNVST LOW, the AD7667 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7667 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (e.g., 50 ) termination should be added
close to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 26.
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
03033-0-026
CNVST
Figure 33. Basic Conversion Timing
t9
t8
RESET
DATA
BUSY
03033-
0-
027
CNVST
Figure 34. RESET Timing
t1
t3
t4
t11
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
03033-
0-
028
CNVST
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7669 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7669AN | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Dual DAC 8-Bit 28-Pin PDIP W |
| AD7669AR | 功能描述:IC I/O PORT 8BIT ANLG 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:LC²MOS 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD7669AR-REEL | 制造商:Analog Devices 功能描述: |
| AD7669ARZ | 功能描述:IC I/O PORT 8BIT ANALOG 28SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:LC²MOS 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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