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| 型號： | AD7608BSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS W/ADC 18BIT 8CH 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 18 b |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.3 V ~ 5.25 V，4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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AD7608
Data Sheet
Rev. A | Page 12 of 32
Pin No.
Type
Mnemonic
Description
11
DI
RESET
Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once tWAKE-UP has
elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If
a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.
12
DI
AA
RDEE
AA
/SCLK
Parallel Data Read Control Input when Parallel Interface is Selected (
AA
RDEE
AA
)/Serial Clock Input when the
Serial Interface is Selected (SCLK). When both
AA
CSEE
AA
and
AA
RDEE
AA
are logic low in parallel mode, the output
bus is enabled.
In parallel mode, two
AA
RDEE
AA
pulses are required to read the full 18 bits of conversion results from each
channel. The first
AA
RDEE
AA
pulse outputs DB[17:2], the second
AA
RDEE
AA
pulse outputs DB[1:0].
In serial mode, this pin acts as the serial clock input for data transfers. The
AA
CSEE
AA
falling edge takes the
data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data
outputs. For further information, see the Conversion Control section.
13
DI
AA
CSEE
Chip Select. This active low logic input frames the data transfer. When both
AA
CSEE
AA
and
AA
RDEE
AA
are logic low
in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the
parallel data bus lines. In serial mode, the
AA
CSEE
AA
is used to frame the serial read transfer and clock out
the MSB of the serial output data.
14
DO
BUSY
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the conversion
data is being latched into the output data registers and is available to be read after a Time t4. Any
data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges
on CONVST A or CONVST B have no effect while the BUSY signal is high.
15
DO
FRSTDATA
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the
AA
CSEE
AA
input is high, the FRSTDATA output pin is in
three-state. The falling edge of
AA
CSEE
AA
takes FRSTDATA out of three-state. In parallel mode, the falling
edge of
AA
RDEE
AA
corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of
AA
RDEE
AA
. In serial mode, FRSTDATA goes high on the falling edge of
AA
CSEE
AA
as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the
AA
CSEE
AA
falling edge. See the Conversion Control section for more details.
22 to 16
DO
DB[6:0]
Parallel Output Data Bits, DB6 to DB0. When
AA
PAREE
AA
/SER SEL = 0, these pins act as three-state parallel
digital output pins. When
AA
CSEE
AA
and
AA
RDEE
AA
are low, these pins are used to output DB8 to DB2 of the
conversion result during the first
AA
RDEE
AA
pulse and output 0 during the second
AA
RDEE
AA
pulse. When
AA
PAREE
AA
/SER
SEL = 1, these pins should be tied to GND.
23
P
VDRIVE
Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).
24
DO
DB7/DOUTA
Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When
AA
PAREE
AA
/SER SEL = 0, this
pin acts as a three-state parallel digital output pin. When
AA
CSEE
AA
and
AA
RDEE
AA
are low, this pin is used to
output DB9 of the conversion result. When
AA
PAREE
AA
/SER SEL = 1, this pin functions as DOUTA and outputs
serial conversion data. See the Conversion Control section for further details.
25
DO
DB8/DOUTB
Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When
AA
PAREE
AA
/SER SEL = 0, this
pin acts as a three-state parallel digital output pin. When
AA
CSEE
AA
and
AA
RDEE
AA
are low, this pin is used to
output DB10 of the conversion result. When
AA
PAREE
AA
/SER SEL = 1, this pin functions as DOUTB and
outputs serial conversion data. See the Conversion Control section for further details.
31 to 27
DO
DB[13:9]
Parallel Output Data Bits, DB13 to DB9. When
AA
PAREE
AA
/SER SEL = 0, these pins act as three-state parallel
digital output pins. When
AA
CSEE
AA
and
AA
RDEE
AA
are low, these pins are used to output DB15 to DB11 of the
conversion result during the first
AA
RDEE
AA
pulse and output zero during the second
AA
RDEE
AA
pulse. When
AA
PAREE
AA
/SER SEL = 1, these pins should be tied to GND.
32
DO/DI
DB14
Parallel Output Data Bit 14 (DB14). When
AA
PAREE
AA
/SER SEL = 0, this pin act as three-state parallel digital
output pin. When
AA
CSEE
AA
and
AA
RDEE
AA
are low, this pin is used to output DB16 of the conversion result during the
first
AA
RDEE
AA
pulse and DB0 of the same conversion result during the second
AA
RDEE
AA
pulse. When
AA
PAREE
AA
/SER
SEL = 1, this pins should be tied to GND.
33
DO/DI
DB15
Parallel Output Data Bit 15 (DB15). When
AA
PAREE
AA
/SER SEL = 0, this pin acts as three-state parallel digital
output pin. This pin is used to output DB17 of the conversion result during the first
AA
RDEE
AA
pulse and
DB1 of the same conversion result during the second
AA
RDEE
AA
pulse. When
AA
PAREE
AA
/SER SEL = 1, this pins
should be tied to GND.
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