參數資料
型號： AD7328BRUZ-REEL7
廠商： Analog Devices Inc
文件頁數： 6/37頁
文件大?。?/td> 0K
描述： IC ADC 12BIT+ SAR 8CHAN 20TSSOP
設計資源： Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
標準包裝： 1,000
系列： iCMOS®
位數： 12
采樣率（每秒）： 1M
數據接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉換器數目： 1
功率耗散（最大）： 30mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數目和類型： 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極
Data Sheet
AD7328
Rev. C | Page 13 of 36
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB above
the last code transition).
Offset Error
This applies to straight binary output coding. It is the deviation
of the first code transition (00 ... 000) to (00 ... 001) from the
ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Gain Error
This applies to straight binary output coding. It is the deviation
of the last code transition (111 ... 110) to (111 ... 111) from the
ideal (that is, 4 × VREF 1 LSB, 2 × VREF 1 LSB, VREF 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input channels.
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale transition
(all 1s to all 0s) from the ideal input voltage, that is, AGND 1 LSB.
Bipolar Zero Code Error Match
This refers to the difference in bipolar zero code error between
any two input channels.
Positive Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. It is the deviation of the
last code transition (011 … 110) to (011 … 111) from the ideal
(that is, 4 × VREF 1 LSB, 2 × VREF 1 LSB, VREF 1 LSB) after
adjusting for the bipolar zero code error.
Positive Full-Scale Error Match
This is the difference in positive full-scale error between any
two input channels.
Negative Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. This is the deviation of
the first code transition (10 … 000) to (10 … 001) from the ideal
(that is, 4 × VREF + 1 LSB, 2 × VREF + 1 LSB, VREF + 1 LSB)
after adjusting for the bipolar zero code error.
Negative Full-Scale Error Match
This is the difference in negative full-scale error between any
two input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
14th SCLK rising edge. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ± LSB, after the end of a conversion.
For the ±2.5 V range, the specified acquisition time is the time
required for the track-and-hold amplifier to settle to within ±1 LSB.
Signal-to-Noise-and-Distortion Ratio
This is the measured ratio of signal to (noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process. The more levels, the smaller the quantization noise.
Theoretically, the signal-to-noise-and-distortion ratio for an
ideal N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
For a 13-bit converter, this is 80.02 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7328, it is defined as
1
6
5
4
3
2
V
THD
2
log
20
)
dB
(
+
=
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.
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