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參數(shù)資料
| 型號： | AD7328BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/37頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+ SAR 8CHAN 20TSSOP |
| 設(shè)計(jì)資源： | Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | iCMOS® |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極 |
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AD7328
Data Sheet
Rev. C | Page 18 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7328.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7328 can be configured to operate in single-ended, true dif-
ferential, or pseudo differential mode. The AD7328 can operate
with either an internal or external reference. In Figure 32, the
AD7328 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The VCC pin can be connected to either a 3 V or 5 V supply voltage.
VDD and VSS are the dual supplies for the high voltage analog
input structures. The voltage on these pins must be equal to or
greater than the highest analog input range selected on the analog
is connected to the supply voltage of the microprocessor. The
voltage applied to the VDRIVE input controls the voltage of the
serial interface. VDRIVE can be set to 3 V or 5 V.
AD7328
VCC
VDD1
SERIAL
INTERFACE
C/P
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
REFIN/OUT
CS
DOUT
VDRIVE
SCLK
DIN
DGND
10F
0.1F
+
10F
0.1F
+
10F
0.1F
+
ANALOG INPUTS:
±10V, ±5V, ±2.5V,
0V TO +10V
+15V
–15V
680nF
VSS1
VCC +2.7V TO +5.25V
1MINIMUM VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
0
48
52-
0
25
10F
0.1F
+
+3V SUPPLY
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7328 has a total of eight analog inputs when operating
in single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7328 in single-
ended mode.
AD73281
VIN+
V+
V–
VDD
VSS
VCC
5V
AGND
1ADDITIONAL PINS OMITTED FOR CLARITY.
0
4852-
026
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7328 can have four true differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including better noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 34 defines the configuration of the true
differential analog inputs of the AD7328.
AD73281
VIN+
VIN–
1
04852-
027
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN pins in
each differential pair (VIN+ VIN). VIN+ and VIN should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × VREF mode, the amplitude of
the differential signal is 20 V to +20 V p-p (2 × 4 × VREF),
regardless of the common mode.
The common mode is the average of the two signals
(VIN+ + VIN)/2
and is therefore the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with reference
voltage. As the reference voltage increases, the common-mode
range decreases. When the differential inputs are driven with an
amplifier, the actual common-mode range is determined by the
amplifier’s output swing. If the differential inputs are not driven
from an amplifier, the common-mode range is determined by
the supply voltage on the VDD supply pin and the VSS supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude 2 × (4 × VREF) to
+2 × (4 × VREF), corresponding to Digital Codes 4096 to +4095.
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