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參數(shù)資料
| 型號(hào)： | AD7265BSUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3CHAN 1MSPS 32TQFP |
| 設(shè)計(jì)資源： | AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 21mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極 |
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AD7265
Rev. A | Page 25 of 28
In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V
AD7265 TO DSP563xx
The connection diagram in Figure 46 shows how the AD7265
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each operates in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).
DRIVE
pin of the AD7265 takes the same supply
voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore the
DSP563xx, if necessary.
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.
SCLK
DSP563xx1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCK0
SC12
SRD1
SRD0
CS
DOUTA
DOUTB
VDRIVE
VDD
SC02
SCK1
04674-039
AD72651
To implement the power-down modes on the AD7265, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
Figure 46. Interfacing the AD7265 to the DSP563xx
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7265BSUZ-REEL7 | 功能描述:IC ADC 12BIT 3CHAN 1MSPS 32TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7266 | 制造商:Analog Devices 功能描述:- Bulk |
| AD7266ACP | 制造商:Analog Devices 功能描述:ADC DUAL SAR 2MSPS 12-BIT SERL 32LFCSP - Bulk |
| AD7266ASU | 制造商:Analog Devices 功能描述:ADC DUAL SAR 2MSPS 12-BIT SERL 32TQFP - Bulk |
| AD7266BCP | 制造商:Analog Devices 功能描述:ADC Dual SAR 2Msps 12-bit Serial 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:DUAL, 2 MSPS, 3-CH SIMULTANEOUS SAMPLING ADC - Bulk |
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