參數(shù)資料
型號(hào)： AD7142ACPZ-1REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/73頁(yè)
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 16 b
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 2.6 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
其它名稱： AD7142ACPZ-1REELDKR
AD7142
Rev. A | Page 39 of 72
REGISTER MAP
The AD7142 address space is divided into three different register
banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59
shows the division of these three banks.
Bank 1 contains control registers, CDC conversion control
registers, interrupt enable registers, interrupt status registers,
CDC 16-bit conversion data registers, device ID registers, and
proximity status registers.
Bank 2 contains the configuration registers used for uniquely
configuring the CIN inputs for each conversion stage. Initialize
the Bank 2 configuration registers immediately after power-up
to obtain valid CDC conversion result data.
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7142 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
05
702
-043
REGISTER BANK 1
ADDR 0x000
ADDR 0x018
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x00B
ADDR 0x017
ADDR 0x7F0
SET UP CONTROL
(1 REGISTER)
CALIBRATION AND SET UP
(4 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
CDC 16-BIT CONVERSION DATA
(12 REGISTERS)
DEVICE ID REGISTER
INVALID DO NOT ACCESS
24
REG
IST
ER
S
REGISTER BANK 2
ADDR 0x080
ADDR 0x0B8
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0C8
ADDR 0x0C0
ADDR 0x0D8
ADDR 0x0D0
96
R
EG
IST
ER
S
REGISTER BANK 3
ADDR 0x0E0
ADDR 0x0B8
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0C8
ADDR 0x0C0
ADDR 0x28F
ADDR 0x0D0
43
2RE
G
IS
T
E
R
S
PROXIMITY STATUS REGISTER
ADDR 0x042
INVALID DO NOT ACCESS
ADDR 0x043
STAGE11 CONFIGURATION
(8 REGISTERS)
STAGE10 CONFIGURATION
(8 REGISTERS)
STAGE9 CONFIGURATION
(8 REGISTERS)
STAGE8 CONFIGURATION
(8 REGISTERS)
STAGE7 CONFIGURATION
(8 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE0 RESULTS
(36 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
STAGE2 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
STAGE4 RESULTS
(36 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE8 RESULTS
(36 REGISTERS)
STAGE9 RESULTS
(36 REGISTERS)
STAGE10 RESULTS
(36 REGISTERS)
STAGE11 RESULTS
(36 REGISTERS)
Figure 59. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
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