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參數(shù)資料
| 型號： | AD7013ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CMOS TIA IS-54 Baseband Receive Port |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 591K |
| 代理商： | AD7013ARS |
–8–
REV. A
AD7013
Limit at T
=
–40
°
C to +85
°
C
Parameter
Units
Description
t
26
Power up Receive to RxCLK
CR13 = 0; Rx Offset Autocalibration On
CR13 = 1; Rx Offset autocalibration Off
Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge
10240t
1
6144t
1
30
85
4t
1
2t
1
–20
2t
1
–20
–10
+10
64t
1
4t
1
–10
+10
12t
1
128t
1
2t
1
+ 20
2t
1
+ 20
ns max
ns max
ns min
ns max
ns
ns min
ns min
ns min
ns max
ns
ns
ns min
ns max
ns min
ns max
ns max
ns max
t
27
t
28
t
29
t
30
t
31
RxCLK Cycle Time; CR10 = 0; 2x Sampling of the Symbol Rate
RxCLK High Pulse Width; CR10 = 0
RxCLK Low Pulse Width; CR10 = 0
RxCLK Rising Edge to RxFRAME Rising Edge
RxCLK to RxFRAME Propagation Delay
RxFRAME Cycle Time; CR10 = 0
RxFRAME High Pulse Width; CR10 = 0
Propagation Delay from RxCLK Rising Edge to RxDATA Valid
t
32
t
33
t
34
t
35
DxCLK Rising Edge to Last Falling Edge of RxCLK
t
36
t
37
3-State to Receive Channel Valid
Receive Channel to 3-State Relinquish Time
(V
AA
= +5 V
±
10%; V
DD
= +5 V
±
10%; AGND = DGND =0 V, f
MCLK
= 6.2208 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
RECEIVE SECTION TIMING
1
t
is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured
number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the
Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance.
MCLK (I)
RxCLK (O)
RxFRAME (O)
RxDATA (O)
t
27
t
29
t
30
t
31
t
32
t
34
t
26
1MSB
DxCLK (O)
CR14
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
0
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
t
35
t
28
Q LSB
1LSB
Q MSB
15-BIT I WORD
1
I/Q FLAG BIT
15-BIT I WORD
I/Q FLAG BIT
t
33
Figure 4. Receive Serial Interface Timing with 2
×
Sampling of the Symbol Rate (CR10 = 0)
RxCLK (O)
RxFRAME (O)
RxDATA (O)
t
36
DxCLK (O)
CR18
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
The last DxCLK edge which is
t
37
The last DxCLK edge which is
3- STATE
ACTIVE
3- STATE
Figure 5. Receive Serial Interface 3-State Timing
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| AD7015AST | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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