- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11674 > AD698SQ (Analog Devices Inc)IC LVDT SGNL COND UNVRSL 24CDIP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD698SQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDT SGNL COND UNVRSL 24CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 信號(hào)調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | LVDT |
| 電流 - 電源： | 15mA |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP |
| 包裝： | 管件 |
REV. B
–6–
AD698
CONNECTING THE AD698
The AD698 can easily be connected for dual or single supply
operation as shown in Figures 7, 8 and 13. The following gen-
eral design procedures demonstrate how external component
values are selected and can be used for any LVDT that meets
AD698 input/output criteria. The connections for the A and B
channels and the A channel comparators will depend on which
transducer is used. In general follow the guidelines below.
Parameters set with external passive components include: exci-
tation frequency and amplitude, AD698 input signal frequency,
and the scale factor (V/inch). Additionally, there are optional
features; offset null adjustment, filtering, and signal integration,
which can be implemented by adding external components.
R1
C1
15nF
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–VS
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+VS
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
33k
1000pF
SIGNAL
REFERENCE
RL
VOUT
100nF
6.8F
–15V
+15V
100nF
6.8F
Figure 7. Interconnection Diagram for Half-Bridge LVDT
and Dual Supply Operation
DESIGN PROCEDURE
DUAL SUPPLY OPERATION
Figure 7 shows the connection method for half-bridge LVDTs.
Figure 8 demonstrates the connections for 3- and 4-wire
LVDTs connected in the series opposed configuration. Both ex-
amples use dual
±15 volt power supplies.
A. Determine the Oscillator Frequency
Frequency is often determined by the required BW of the sys-
tem. However, in some systems the frequency is set to match
the LVDT zero phase frequency as recommended by the
manufacturer; in this case skip to Step 4.
1. Determine the mechanical bandwidth required for LVDT
position measurement subsystem, fSUBSYSTEM. For this ex-
ample, assume fSUBSYSTEM = 250 Hz.
2. Select minimum LVDT excitation frequency approximately
10
× f
SUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.
3. Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. The Schaevitz E100, for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.
4. Select excitation frequency determining component C1.
C1
= 35 FHz/f
EXCITATION
R1
C1
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–VS
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+VS
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
1000pF
SIGNAL
REFERENCE
RL
VOUT
100nF
6.8F
–15V
+15V
100nF
6.8F
1M
AB
C
D
PHASE
LAG/LEAD
NETWORK
RT
AB
CD
PHASE LEAD
RS
C
RS
RT
A
B
CD
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = RS// (RS + RT)
Figure 8. AD698 Interconnection Diagram for Series
Opposed LVDT and Dual Supply Operation
B. Determine the Oscillator Amplitude
Amplitude is set such that the primary signal is in the 1.0 V to
3.5 V rms range and the secondary signal is in the 0.25 V to
3.5 V rms range when the LVDT is at its mechanical full-scale
position. This optimizes linearity and minimizes noise suscepti-
bility. Since the part is ratiometric, the exact value of the excita-
tion is relatively unimportant.
5. Determine optimum LVDT excitation voltage, VEXC. For a
4-wire LVDT determine the voltage transformation ratio,
VTR, of the LVDT at its mechanical full scale. VTR =
LVDT sensitivity
× Maximum Stroke Length from null.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of volts output per volts input per inch dis-
placement. The E100 has a sensitivity of 2.4 mV/V/mil. In
the event that LVDT sensitivity is not given by the manufac-
turer, it can be computed. See section on determining LVDT
sensitivity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J3B-IY-F2 | CONVERTER MOD DC/DC 95V 50W |
| MS27467T25A29PA | CONN PLUG 29POS STRAIGHT W/PINS |
| 2-227079-2 | CONN PLUG BNC 50 OHM DUAL CRIMP |
| MS27467E25A29PA | CONN PLUG 29POS STRAIGHT W/PINS |
| MS27473E24F61SB | CONN PLUG 61POS STRAIGHT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD-6B | 制造商:Altas 功能描述: |
| AD6C101 | 制造商:SSOUSA 制造商全稱:SSOUSA 功能描述:1 Form A Solid State Relay |
| AD6C101Q1STR | 制造商:SOLID STAT 功能描述:NEW |
| AD6C111 | 制造商:SSOUSA 制造商全稱:SSOUSA 功能描述:1 Form A Solid State Relay |
| AD6C111-E | 制造商:SSOUSA 制造商全稱:SSOUSA 功能描述:1 Form A Solid State Relay |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。