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參數(shù)資料
| 型號： | AD698SQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC LVDT SGNL COND UNVRSL 24CDIP |
| 標準包裝： | 1 |
| 類型： | 信號調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | LVDT |
| 電流 - 電源： | 15mA |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP |
| 包裝： | 管件 |
AD698
REV. B
–7–
b. Full-scale core displacement from null, d
S
× d = VTR and also equals the ratio A/B at mechanical full
scale. The VTR should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
VOUT = S
× d × 500 A × R2
VOUT is measured with respect to the signal reference,
Pin 21, shown in Figure 7.
Solving for R2,
R2
=
VOUT
S
× d × 500 A
(1)
For VOUT =
±10 V full-scale range (20 V span) and d = ±0.1
inch full-scale displacement (0.2 inch span)
R2
=
20V
2.4
× 0.2 × 500 A =
83. 3 k
VOUT as a function of displacement for the above example is
shown in Figure 10.
+10
+0.1d (INCHES)
–0.1
–10
V
OUT
(VOLTS)
Figure 10. VOUT (
±10 V Full Scale) vs. Core Displace-
ment (
±0.1 Inch)
E. Optional Offset of Output Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
VOS = 1.2 V × R2 ×
1
R3
+ 2 k
–
1
R4
+ 2 k
(2)
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set VOUT to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
+5
+0.1d (INCHES)
–0.1
–5
V
OUT
(VOLTS)
Figure 11. VOUT (±5 V Full Scale) vs. Core Displacement
(
±0.1 Inch)
This will produce a response shown in Figure 11.
In Equation (2) set VOS = 5 V and solve for R3 and R4. Since a
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
R3
= 1.2 × R2
VOS
–2 k
= 7.02 k
Multiply the primary excitation voltage by the VTR to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of
±0.1 inch, the VTR = 0.0024 V/V/Mil × 100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms
× 0.24 =
0.84 V rms, which is in the acceptable range.
Conversely the VTR may be measured explicitly. With the
LVDT energized at its typical drive level VPRI, as indicated
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output VSEC of
the secondary. Compute the LVDT voltage transformation
ratio, VTR. VTR = VSEC//VPRI. For the E100, VSEC = 0.72 V
for VPRI = 3 V. VTR = 0.24.
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VTR should also be re-
duced by 1/2 for the purpose of component selection.
Check the power supply voltages by verifying that the peak
values of VA and VB are at least 2.5 volts less than the volt-
ages at +VS and –VS.
6. Referring to Figure 9, for VS = ± 15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 9.
30
15
0
0.01
0.1
1k
100
10
1
5
10
20
25
V rms
R1 – k
V
EXC
–
V
rm
s
Figure 9. Excitation Voltage VEXC vs. R1
7. C2, C3 and C4 are a function of the desired bandwidth of
the AD698 position measurement subsystem. They should
be nominally equal values.
C2 = C3 = C4 = 10
–4 Farad Hz/f
5UBSYSTEM (Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10
-4 Farad Hz/250 Hz = 0.4
F
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
D. Set the Full-Scale Output Voltage
8. To compute R2, which sets the AD698 gain or full-scale
output range, several pieces of information are needed:
a. LVDT sensitivity, S
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