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參數(shù)資料
| 型號(hào)： | AD693AQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSMITTER 4-20MA 20-CDIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 類型： | 信號(hào)調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 3 線 |
| 電流 - 電源： | 20mA |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-CDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 798 (CN2011-ZH PDF) |
AD693
REV. A
–12–
C1050a–9–10/87
PRINTED
IN
U.S.A.
Error it is necessary to add an error of only (5 – 2)
× V
OS to the
error budget. Note that span error may by reduced to zero with
the span trim, leaving only the offset and nonlinearity of the
AD693.
EXAMPLE I
The AD693 is configured as a 4-20mA loop powered transmitter
with a 60 mV FS input. The inputs are driven by a differential
voltage at 2 V common mode with a 300
balanced source
resistance. A 24 V loop supply is used with a 500
metering
resistance. (See Table IV below.)
Trimming the offset and span for your application will remove
all span and offset errors except the nonlinearity of the AD693.
Table IV. Example 1
OFFSET ERRORS
IZ
Already included in the TUE spec .
0.0
V
PSRR
PSRR = 5.6
V/V; (|24 V – 24 V| + [| 500 – 250 × 4 mA]) × 5.6 V/V =5.6 V
VLOOP = 24 V
RL = 500
I
Z = 4 mA
CMRR
CMRR = 30
V/V; |2 V –3.1 V| × 30 V/V =
33.0
V
VCM = 2 V
IOS
IOS = 3 nA, RS = 300
; 300 × 3 nA =
0.9
V
Total Additional Error at 4 mA
39.5
V
As % of full scale; (39.5
V × 0.2666 A/V)/20 mA × 100% =
0.053 % of FS
SPAN ERRORS
XSE
Already included in the TUE spec
0.0
V
XPSRR
PSRR = 5.6
V/V; (|500 – 250 | × 16 mA) × 5.6 V/V =
22.4
V
RL = 500
, I
S = 16 mA
XCMRR
XCMRR = 0.06%/V; |2 V – 3. 1 V| × 60 mV × 0.06%/V =
39.6
V
VCM = 2 V, VSPAN = 60 mV
IDIFF
VSPAN = +60 mV; 300
× 2 × 20 nA
12.0
V
IDIFF/ + In = 2
from Figure 2)
XNL
Already included in the TUE
0.0
V
Total Additional Span Error at Full Scale
74.0
V
Total Additional Error at Full Scale; OFFSET + SPAN = 39.5
V + 74.0 V =
113.5
V
As % of Full Scale; (113.5
V × 0.2666A V)/20 mA × 100% =
0.151% of FS
New Total Unadjusted Error @ FS; TUE + ADDITIONAL = 0.5% +0.151% =
0.651% of FS
and an input common-mode voltage of 3.1 V. The expressions
below calculate errors due to deviations from these nominal
conditions.
The total error at zero consists only of offset errors. The total
error at full scale consists of the offset errors plus the span
errors. Adding the above errors in this manner may result in an
error as large as 0.8% of full scale, however, as a rule, the
AD693 performs better as the span and offset errors do not tend
to add worst case. The specification “Total Unadjusted Error,”
(TUE), reflects this and gives the maximum error as a % of full
scale for any point in the transfer function when the device is
operated in one of its preset spans, with no external trims. The
TUE is less than the error you would get by adding the span
and offset errors worst case.
Thus, an alternative way of calculating the total error is to start
with the TUE and add to it those errors that result from
operation of the AD693 with a load resistance, loop supply
voltage, or common-mode input voltage different than specified.
(See Example 1 below.)
ERROR BUDGET FOR SPANS LESS THAN 30 mV
An accommodation must be made to include the input voltage
offset of the signal amplifier when the span is adjusted to less
than 30 mV. The TUE and the Zero Current Error include the
input offset voltage contribution of the signal amplifier in a gain
of 2. As the input offset voltage is multiplied by the gain of the
signal amplifier, one must include the additional error when the
signal amplifier is set to gains greater than 2.
For example, the 300K span thermocouple application discussed
previously requires a 12.207 mV input span; the signal amplifier
must be adjusted to a gain of approximately 5. The loop trans-
conductance is now 1.333 A/V, (5
× 0.2666 A/V). Calculate the
total error by substituting the new values for the transconductance
and span into the equations in Table III as was done in Example
I. The error contribution due to VOS is 5
× V
OS, however, since
2
× V
OS is already included in the TUE and the Zero Current
E-20A
20-Terminal Leadless Chip Carrier
D-20
20-Lead Side Brazed Ceramic DIP
Q-20
20-Lead Cerdip
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
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