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參數(shù)資料
| 型號(hào)： | AD6654CBC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 70/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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AD6654
Rev. 0 | Page 72 of 88
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has four address locations.
The memory map is roughly divided into four regions: global
register map (Address 0x00 to Address 0x0B), input port
register map (Address 0x0C to Address 0x67), channel register
map (Address 0x68 to Address 0xBB), and output port register
map (Address 0xBC to Address 0xE7). The channel register
map is shared by all six channels, and access to individual
channels is given by the channel I/O access control register
(Address 0x02).
In the memory map in Table 28, the addresses are given in the
right column. The column with the heading Byte 0 has the
address given in the right column. The column Byte 1 has the
address given by 1 more than the address listed in the right
column (address offset of 1). Similarly, the address offset for the
Byte 2 column is 2, and for the Byte 3 column is 3. For example,
the second row lists 0x04 as the address in the right column.
The pin synchronization configuration register has Address
0x04, the soft synchronization configuration register has
Address 0x05, and Address 0x06 and Address 0x07 are
reserved/open.
BIT FORMAT
All registers are in little-endian format. For example, if a register
takes 24 bits or three address locations, then the most signifi-
cant byte is at the highest address location and the least
significant byte is at a lowest address location. In all registers,
the least significant bit is Bit 0 and the most significant bit is
Bit 7. For example, the NCO frequency <31:0> register is
32 bits wide. Bit 0 (LSB) of this register is written at Bit 0 of
Address 0x70 and Bit 32 (MSB) of this register is written at
Bit 7 of Address 0x73.
When referring to a register that takes up multiple address
locations, it is referred to by the address location of the most
significant byte of the register. For example, the text reads,
“Port A dwell timer at Address 0x2A.” Note that only the four
most significant bits of this register are at this location, and this
register also takes up Addresses 0x29 and 0x28.
OPEN LOCATIONS
All locations marked as open are currently not used. When
required, these locations should be written with 0s. Writing to
these locations is required only when part of an address location
is open (for example, Address 0x78). If the whole address
location is open (for example, Address 0x00), then this address
location does not need to be written. If the open locations are
read back using the microport or serial port, the readback value
is undefined (each bit can be independently 1 or 0), and these
bits have no significance.
If an address location has more than one register or has one
register with some open bits, then the order of these registers is
as given in Table 28. For example, Address 0x33 reads
Open <7:5>, Port A Signal Monitor <4:0>.
The open <7:5> is located at Bits <7:5> and the Port A signal
monitor <4:0> is located at Bits <4:0>.
Another example is Address 0x35:
Open <15:10>, Port A Upper Threshold <9:0>
Here, Bits <7:2> of Address 0x35 are open <15:10>. Bits <1:0>
of Address 0x35 and Bits <7:0> of Address 0x34 make up the
Port A upper threshold <9:0> register (Bit 1 of Address 0x35 is
the MSB of the Port A upper threshold register).
DEFAULT VALUES
Coming out of reset, some of the address locations (but not all)
are loaded with default values. When available, the default
values for the registers are given in the table. If the default value
is not listed, then the address location is in an undefined state
(Logic 0 or Logic 1) on RESET.
LOGIC LEVELS
In the explanation of various registers, “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
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參數(shù)描述 |
|---|---|
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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