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參數(shù)資料
| 型號(hào)： | AD6654CBC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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AD6654
Rev. 0 | Page 48 of 88
OUTPUT DATA ROUTER
The output data router circuit precedes the six AGCs of the
final output block and immediately follows interpolating half-
band filters. This block consists of two subblocks. The first
block is responsible for combining (interleaving) data from
more than one channel into a single stream of data. The second
block performs complex filter completion, as explained later in
this section. The combined data is passed on to the AGCs.
STREAM
CONTROL
PARALLEL
PORT A
PARALLEL
PORT C
PARALLEL
PORT B
AGC0
CH0
AGC1
CH1
AGC2
CH2
AGC3
CH3
AGC4
CH4
AGC5
CH5
05156-044
Figure 55. Block Diagram of the Output Data Router
INTERLEAVING DATA
In some cases, filtering using a single channel is insufficient. For
such setups, it is advantageous to combine the filtering
resources of multiple channels rather than using filtering
resources from a single channel.
Multiple channels can be set up to co-process the ADC input
port data with the same NCO and filter setups. The decimation
phase values in one of the RCF filters are set such that the
channel’s filters are exactly out of phase with each other. In the
data router, these multiple channels are interleaved (combined)
to form a single stream of data. Because each individual channel
is decimated more than it would have been if a single channel
were filtering, more number-of-filter taps can be calculated.
This is best illustrated with an example:
Two channels need to work together to produce a filter at an
output rate of 9.216 MHz, when the input rate is 92.16 MHz.
Each channel is decimated by a factor of 20 (total decimation)
to achieve the desired output rate of 4.608 MHz each. This
compares to a decimation of 10, if a single channel were
working towards filtering.
The same coefficients are programmed into both of the
channels’ RCF filters, and the decimation phases are set to 0
and 1. The decimation phases can be set to 0 for one channel
and 1 for the second channel in the pair. This causes the first
channel to produce the even outputs of the filter, and the
second to produce the odd outputs of the filter. The streams
are then recombined (interleaved) to produce the desired
9.216 MHz output rate. The benefit is that now each channel’s
RCF has time to calculate twice as many taps, because it has a
lower output rate.
The interleaving function is a simple time-multiplexing func-
tion, with lower data rate on the input side and higher data rate
on the output side. The output data rate is the sum of all input
stream data rates that are combined.
The channels that need to be combined are programmable with
sufficient flexibility. Table 24 gives the combinations that are
possible using a 4-bit word (stream control bits) in the Parallel
Port Control 2 register.
Table 24. Stream Control Bit Combinations and Selections
Stream
Control Bits
Output Streams
Number of
Streams
0000
Ch 0, Ch 1 combined; Ch 2, Ch 3,
Ch 4, Ch 5 independent
5
0001
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4, Ch 5 independent
4
0010
Ch 0, Ch 1, Ch 2, Ch 3 combined;
Ch 4, Ch 5 independent
3
0011
Ch 0, Ch 1, Ch 2, Ch 3, Ch 4
combined; Ch 5 independent
2
0100
Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5
combined
1
0101
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4, Ch 5 combined
2
0110
Ch 0, Ch 1 combined; Ch 2, Ch 3
combined; Ch 4, Ch 5 combined
3
0111
Ch 0, Ch 1 combined; Ch 2, Ch 3
combined; Ch 4, Ch 5 independent
3
1000
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4 combined; Ch 5 independent
3
1001
Ch 0, Ch 1, Ch 2, Ch 3 combined;
Ch 4, Ch 5 combined
2
Any other
state
Independent channels
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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