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參數(shù)資料
| 型號： | AD6650PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Diversity IF to Baseband GSM/EDGE Narrowband Receiver |
| 中文描述： | 多樣性IF到基帶的GSM / EDGE窄帶接收器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 594K |
| 代理商： | AD6650PCB |
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Preliminary Technical Data
GENERAL TIMING CHARACTERISTICS
Parameter (Conditions)
CLK Timing Requirements:
t
CLK
CLK Period
t
CLKL
CLK Width Low
t
CLKH
CLK Width High
/RESET Timing Requirements:
t
RESL
/RESET Width Low
SYNC Timing Requirements:
t
SS
SYNC to
↑
CLK Setup Time
t
HS
SYNC to
↑
CLK Hold Time
Master Mode Serial Port Timing Requirements (SBM=1):
Switching Characteristics
2
t
DSCLK1
↑
CLK to
↑
SCLK Delay (divide by 1)
t
DSCLKH
↑
CLK to
↑
SCLK Delay (for any other divisor)
t
DSCLKL
↑
CLK to
↓
SCLK Delay (divide by 2 or even #)
t
DSCLKLL
↓
CLK to
↓
SCLK Delay (divide by 3 or odd #)
t
DSDFS
↑
SCLK to SDFS Delay
t
DSDO
↑
SCLK to SDO Delay
t
DSD1
↑
SCLK to SD1 Delay
t
DSDR
↑
SCLK to DR Delay
Slave Mode Serial Port Timing Requirements (SBM=0):
Switching Characteristics
2
t
SCLK
SCLK Period
t
SCLKL
SCLK low time (when SDIV=1, divide by 1)
t
SCLKH
SCLK high time (when SDIV=1, divide by 1)
t
DSDO
↑
SCLK to SDO Delay
t
DSD1
↑
SCLK to SD1 Delay
t
DSDR
↑
SCLK to DR Delay
Input Characteristics
t
SSF
SDFS to
↑
SCLK Setup Time
t
HSF
SDFS to
↑
SCLK Hold Time
1
All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V.
2
The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1). The Slave serial port’s (SCLK)
operating frequency is limited to 52 MHz.
3
Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS
4
(C
LOAD
=40pF on all outputs unless otherwise specified)
AD6650
REV. PrJ 02/27/2003
6
Temp
Full
Full
Full
Full
Full
Full
Test
Level
I
IV
IV
IV
IV
IV
Min
9.6
30
AD6650
Typ
0.5 x t
CLK
0.5 x t
CLK
Max
Units
ns
ns
ns
ns
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.9
4.4
3.25
3.8
13.4
14.0
6.7
6.9
ns
ns
ns
ns
ns
ns
ns
ns
3.02
2.7
2.6
2.7
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
16.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
6.8
6.8
6.9
2.6
-1.15
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|---|---|
| AD6650BBC1 | Diversity IF to Baseband GSM/EDGE Narrowband Receiver |
| AD6652 | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652BBC | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652BC | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652PCB | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
相關代理商/技術參數(shù) |
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|---|---|
| AD6652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652BBC | 制造商:Analog Devices 功能描述:IF to Baseband Diversity Receiver 256-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC IF TO BASEBAND RCVR SMD 6652 |
| AD6652BBCZ | 功能描述:IC IF TO BASEBAND RCVR 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD6652BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
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