參數(shù)資料
型號(hào)： AD6650BBC1
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 594K
代理商： AD6650BBC1
Preliminary Technical Data
6 can be used to enable syncs to individual blocks in the
channels.
AD6650
REV. PrJ 02/27/2003
23
Data Address Registers
External Address [2-0] form the data registers DR2, DR1
and DR0 respectively. All internal data words have widths
that are less than or equal to 20 bits. Accesses to External
Address [0] DR0 trigger an internal access to the AD6650
based on the address indicated in the ACR and CAR. Thus
during writes to the internal registers, External Address [0]
DR0 must be written last. At this point data is transferred to
the internal memory indicated in A[9:0]. Reads are
performed in the opposite direction. Once the address is set,
External Address [0] DR0must be the first data register read
to initiate an internal access. DR2 is only 4 bits wide. Data
written to the upper 4 bits of this register will be ignored.
Likewise reading from this register will produce only 4
LSBs.
Write Sequencing
Writing to an internal location is achieved by first writing
the upper two bits of the address to bits 1 through 0 of the
ACR. Bits 7:2 may be set to select the channel as indicated
above. The CAR is then written with the lower eight bits of
the internal address (it doesn’t matter if the CAR is written
before the ACR as long as both are written before the
internal access). Data register 2, (DR2) and register 1 (DR1)
must be written first because the write to data register DR0
triggers the internal access. Data register DR0 must always
be the last register written to initiate the internal write.
Read Sequencing
Reading from the micro port is accomplished in the same
manner. The internal address is set up the same way as the
write. A read from data register DR0 activates the internal
read, thus register DR0 must always be read first to initiate
an internal read followed by DR1and DR2. This provides
the 8 LSBs of the internal read through the micro port
(D[7:0]). Additional data registers can be read to read the
balance of the internal memory.
Read/Write Chaining
The micro port of the AD6650 allows for multiple accesses
while /CS is held low (/CS can be tied permanently low if
the micro port is not shared with additional devices). The
user can access multiple locations by pulsing the /WR or
/RD line and changing the contents of the external three bit
address bus. External access to the external registers of
Table 2 is accomplished in one of two modes using the /CS,
/RD, /WR, and MODE inputs. The access modes are Intel
Non-Multiplexed mode and Motorola Non-Multiplexed
mode. These modes are controlled by the MODE input
(MODE=0 for INM, MODE=1 for MNM). /CS, /RD, and
/WR control the access type for each mode.
Programming Modes
The AD6650 can be programmed using several different
modes. These modes include two micro-port modes, Intel
Non-Multiplexed mode and Motorola Non-Multiplexed
Mode, and a serial port mode, I
2
C. The programming mode
can be selected by writing the appropriate 3-bit word to the
mode pins. The following table identifies which word
selects the desired mode.
Mode [2:0]
Comment:
000
Micro-Port Intel Non-Multiplexed
Mode
001
Micro-Port Motorola Non-Multiplexed
Mode
010
Reserved
011
Reserved
100
I
2
C
101
Reserved
110
Reserved
111
Reserved
Intel Non-Multiplexed Mode (INM)
Setting the mode word bits to 000 will enable the AD6650
microprocessor in INM mode. The access type is controlled
by the user with the /CS, /RD (/DS), and /WR (RW) inputs.
The RDY (/DTACK) signal is produced by the micro port to
communicate to the user that an access has been completed.
RDY (/DTACK) goes low at the start of the access and is
released when the internal cycle is complete. See the timing
diagrams for both the read and write modes in the
Specifications.
Motorola Non-Multiplexed Mode (MNM)
Setting the mode word bits to 001 will enable the AD6650
microprocessor in MNM mode. The access type is
controlled by the user with the /CS, /DS (/RD), and RW
(/WR) inputs. The /DTACK (RDY) signal is produced by
the micro port to communicate to the user that an access has
been completed. /DTACK (RDY) goes low when an
internal access is complete and then will return high after
/DS (/RD) is de-asserted. See the timing diagrams for both
the read and write modes in the Specifications.
I
2
C Control
I
2
C programming is selected by setting MODE =100. I
2
C is
a two-line bi-directional serial interface specification
developed by Phillips that the AD6650 uses to program the
control registers/ coefficient memory address space. It uses
one data line (SDA) and one clock line (SCL) to transfer
data between a master device and a slave device. The
AD6650 can only act as an I
2
C slave, so a master device is
always needed to program it in I
2
C mode. I
2
C data transfers
or the AD6650 comply with the Standard-mode transfer, up
to 100 kHz. An I
2
C bus can be multi-master and/or multi-
slave relying on the wired-and function of the devices
connected to it to indicate that the bus is free. To comply
with this, the I
2
C pins on the AD6650 are open-drain
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