參數(shù)資料
型號(hào)： AD6650
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 594K
代理商： AD6650
Preliminary Technical Data
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1
AD6650
REV. PrJ 02/27/2003
7
MICROPROCESSOR PORT, MODE INM (MODE=0)
MODE INM Write Timing:
t
SC
t
HC
t
HWR
/WR(RW) to RDY(/DTACK) Hold Time
t
SAM
Address/Data to /WR(RW) Setup Time
t
HAM
Address/Data to RDY(/DTACK) Hold Time
t
DRDY
/WR(RW) to RDY(/DTACK) Delay
t
ACC
/WR(RW) to RDY(/DTACK) High Delay
MODE INM Read Timing:
t
SC
t
HC
t
SAM
Address to /RD(/DS) Setup Time
t
HAM
Address to Data Hold Time
t
ZD
Data Tri-state Delay
t
DD
RDY(/DTACK) to Data Delay
t
DRDY
/RD(/DS) to RDY(/DTACK) Delay
t
ACC
/RD(/DS) to RDY(/DTACK) High Delay
MICROPROCESSOR PORT, MODE MNM (MODE=1)
Temp
Test
Level
Min
AD6650
Typ
Max
Units
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Test
Level
5.5
1.0
8.0
-0.5
7.0
4.0
4*t
CLK
4.0
2.0
0.0
7.0
4.0
4*t
CLK
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5*t
CLK
7*t
CLK
Max
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
AD6650
Typ
Units
MODE MNM Write Timing:
t
SC
t
HC
t
HDS
t
HRW
t
SAM
t
HAM
t
DDTACK
t
ACC
MODE MNM Read Timing:
t
SC
t
HC
t
HDS
t
SAM
t
HAM
t
ZD
t
DD
t
DDTACK
t
ACC
MODE I
2
C Timing:
t
DSCL
t
DSDA
t
SSCL
1
All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V.
2
The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1)
3
Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS
4
(C
LOAD
=40pF on all outputs unless otherwise specified)
5
There is no hold time for SDA because as this waits for a negative transition (
↓
) on SCL to transition.
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
/DS(/RD) to /DTACK(RDY) Hold Time
RW(/WR) to /DTACK(RDY) Hold Time
Address/Data To RW(/WR) Setup Time
Address/Data to RW(/WR) Hold Time
/DS(/RD) to /DTACK(RDY) Delay
RW(/WR) to /DTACK(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
5.5
1.0
8.0
8.0
-0.5
7.0
4*t
CLK
4.0
2.0
8.0
0.0
7.0
4*t
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5*t
CLK
7*t
CLK
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
/DS(/RD) to /DTACK(RDY) Hold Time
Address to /DS(/RD) Setup Time
Address to Data Hold Time
Data Tri-State Delay
/DTACK(RDY) to Data Delay
/DS(/RD) to /DTACK(RDY) Delay
/DS(/RD) to /DTACK(RDY) Low Delay
↑
SCL to SDA Delay
SDA to
↑
SCL Delay
↑
CLK to
↑
SCL Delay
61
57
5
5
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