參數(shù)資料
型號： AD6650
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁數(shù)： 2/28頁
文件大?。?/td> 594K
代理商： AD6650
Preliminary Technical Data
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .xx
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . .. .xx
SPECIFICATIONS/CHARACTERISTICS . . . . . .. . . . . . xx
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .xx
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . xx
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xx
EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . .xx
AGC LOOP.......................................................................xx
DC CORRECTION...........................................................xx
FOURTH ORDER CASCADED INTEGRATOR COMB
FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
CIC4 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
INFINITE IMPULSE RESPONSE xx
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . .xx
RCF Decimation Register . . . . . . .. . . . . .. . . . . xx
RCF Decimation Phase . . . . .. . . . . . . . . . . . . . xx
RCF Filter Length . . . . . .. . . . . . . . . . . . . . . . . .xx
RCF Output Scale Factor and Control Register . xx
USER-CONFIGURABLE BUILT-IN SELF-TEST
CHANNEL BIST...........................................xx
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . .xx
Start . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx
SERIAL OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . .xx
Serial Output Data Format . . . . . . . . . . . . . . . . . xx
Serial Data Frame (Serial Bus Master) .. . . . . . . . xx
Serial Data Frame (Serial Cascade) . . . . . . . . . xx
Configuring the Serial Ports . . . . . . . .. . . . . . . xx
Serial Port Data Rate . . . . . . . . . .. . . . . . . . . . . . xx
Serial Slave Operation . . . . . . . . . .. . . . . . . . . . . xx
Serial Ports Cascaded . . . . . . . .. . . . . . . . . . . . . . xx
Serial Output Frame Timing (Master and Slave) xx
Serial Port Timing Specifications . . . . . . ... . . . . xx
SCLK . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . xx
SDO0 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . xx
SDO1 . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx
SDFS . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . xx
Serial Word Length . . . . . .. . . . . . . . . . . . . . . . . xx
SDFS Mode . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx
Mapping RCF Data to the BIST Registers . . . .. . xx
0x00: Clock Divider Control . .. . .xx
0x01-0x05: PLL Register[4:0] . . . . . . .. . . . . .. . xx
0x06: Clamp Control............................................xx
AD6650
REV. PrJ 02/27/2003
2
0x07: Aux DAC A ...............................................xx
0x08: Aux DAC B ................................................xx
0x09: Aux DAC Control.......................................xx
0x0A: ADC Dither Control.................................xx
0x0B: DC Correction BW.....................................xx
0x0C: DC Correction Control...............................xx
0x0D-0x14: AGC Control[7:0]............................xx
0x15: Start Hold-Off Counter...............................xx
0x16: CIC4 Decimation.......................................xx
0x17: CIC4 Scale.................................................xx
0x18: IIR Control Register...................................xx
0x19: RCF Decimation Register..........................xx
0x1A: RCF Decimation Phase..............................xx
0x1B: RCF Coefficient Offset..............................xx
0x1C: RCF Taps....................................................xx
0x1D: RCF Scale Register...................................xx
0x1E-0x1F: BIST For A-I/Q.................................xx
0x20-0x21: BIST for B-I/Q..................................xx
0x22: Serial Control Register...............................xx
0x23-0x29: Reserved............................................xx
0x30-0x5F: Coefficient Memory.........................xx
0x60-0xFF: Reserved...........................................xx
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . xx
External Memory Map . . . . . .. . . . . . . . . . . . . . . xx
Access Control Register (ACR) . . . . .. . . . . . . . . xx
External Memory Map . . . . . . ... . . . . . . . . . . . . xx
Channel Address Register (CAR) . .. . . . . . . . . . xx
SOFT_SYNC Control Register . .. . . . . . . . . . xx
PIN_SYNC Control Register . . . ... . . . . . . . . . xx
SLEEP Control Register . . . . . . .. . . . . . . . . . . . xx
Data Address Registers . . . . . . .. . . . . . . . . . . . . xx
Write Sequencing . . . . . . . .. . . . . . . . . . . . . . . . . xx
Read Sequencing . . . . . . . .. . . . . . . . . . . . . . . . . xx
Read/Write Chaining . . . . .. . . . . . . . . . . . . . . . . xx
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . xx
Motorola Nonmultiplexed Mode (MNM) ... . . . . xx
I
2
C PORT CONTROL
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . .xx
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . .. . . . .xx
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . xx
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . xx
OUTLINE DIMENSIONS . . . . . . . . . . . . . .. . . . . xx
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參數(shù)描述
AD6650/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver
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