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參數(shù)資料
| 型號： | AD5737ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/44頁 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD 12BIT CUR 64-LFCSP |
| 標準包裝： | 1 |
| 設(shè)置時間： | 15µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5737
Rev. C | Page 33 of 44
DEVICE FEATURES
FAULT OUTPUT
The AD5737 is equipped with a FAULT pin, an active low,
open-drain output that allows several AD5737 devices to be
connected together to one pull-up resistor for global fault
detection. The FAULT pin is forced active by any one of the
following fault conditions:
The voltage at IOUT_x attempts to rise above the compliance
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with windowed
limits because this requires an actual output error before
the FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive
capability. Thus, the FAULT output is activated slightly
before the compliance limit is reached.
An interface error is detected due to a PEC failure (see the
Packet Error Checking section).
The core temperature of the AD5737 exceeds approxi-
mately 150°C.
The IOUT_x fault, PEC error, and over temp bits of the status
register are used in conjunction with the FAULT output to
inform the user which fault condition caused the FAULT
output to be activated.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the DAC data register is
operated on by a digital multiplier and adder controlled by the
contents of the gain and offset registers; the calibrated DAC
data is then stored in the DAC input register (see Figure 52).
DAC
INPUT
REGISTER
DAC
DAC DATA
REGISTER
GAIN (M)
REGISTER
OFFSET (C)
REGISTER
10067-
075
Figure 52. Digital Offset and Gain Control
Although Figure 52 indicates a multiplier and adder for each
channel, the device has only one multiplier and one adder,
which are shared by all four channels. This design has impli-
cations for the update speed when several channels are updated
at once (see Table 3).
When data is written to the gain (M) or offset (C) register, the
output is not automatically updated. Instead, the next write to
the DAC channel uses the new gain and offset values to perform
a new calibration and automatically updates the channel.
The output data from the calibration is routed to the DAC input
register. This data is then loaded to the DAC, as described in the
Serial Interface section. Both the gain register and the offset
register have 12 bits of resolution. The correct order to calibrate
the gain and offset is to first calibrate the gain and then calibrate
the offset.
The value (in decimal) that is written to the DAC input register
can be calculated as follows:
11
12
2
)
1
(
+
×
=
C
M
D
Code
r
DACRegiste
(1)
where:
D is the code loaded to the DAC data register of the
DAC channel.
M is the code in the gain register (default code = 212 1).
C is the code in the offset register (default code = 211).
STATUS READBACK DURING A WRITE
The AD5737 can be configured to read back the contents of
the status register during every write sequence. This feature is
enabled using the STATREAD bit in the main control register.
When this feature is enabled, the user can continuously monitor
the status register and act quickly in the case of a fault.
When status readback during a write is enabled, the contents
of the 16-bit status register (see Table 32) are output on the SDO
pin, as shown in Figure 5.
When the AD5737 is powered up, the status readback during a
write feature is disabled. When this feature is enabled, readback
of registers other than the status register is not available. To read
back any other register, clear the STATREAD bit before following
the readback sequence (see the Readback Operation section).
The STATREAD bit can be set high again after the register read.
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge sensitive input that allows the
output to be cleared to a preprogrammed 12-bit code. This code
is user-programmable via a per-channel 12-bit clear code register.
For a channel to be cleared, set the CLR_EN bit in the DAC
control register for that channel. If the clear function on a
channel is not enabled, the output remains in its current state,
independent of the level of the CLEAR pin.
When the CLEAR signal returns low, the relevant outputs remain
cleared until a new value is programmed to them.
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| AD573JD | 功能描述:IC ADC 10BIT SAR REG 20-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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| AD573JNZ | 功能描述:IC ADC 10BIT SAR REGISTER 20-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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