參數(shù)資料
型號(hào)： AD5379
廠商： Analog Devices, Inc.
英文描述： 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC
中文描述： 40通道，14位，并行和串行輸入，雙極性電壓輸出DAC
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 393K
代理商： AD5379
AD5379
V
BIAS
FUNCTION
The AD5379 has an on-chip voltage generator that provides a
bias voltage of 4.25 V (min). The V
BIAS
pin is provided for
bypassing and overdriving purposes only. It is not intended to
be used as a supply or a reference. If V
REF
(+) > 4.25 V, V
BIAS
must
be pulled high externally to an equal or higher potential (such
as 5 V). The external voltage source should be capable of driving
a 50 μA (typical) current sink load.
Rev. 0 | Page 19 of 28
REFERENCE SELECTION
The voltages applied to V
REF
(+) and V
REF
() determine the
output voltage range and span on VOUT0 to VOUT39. If the
offset and gain features are not used (m and c are left at their
power-on values), the reference levels required can be calculated
as follows:
V
REF
(+)
min
= (
VOUT
max
VOUT
min
)/3.5
V
REF
()
max
= (
AGND
+
VOUT
min
)/2.5
If the offset and gain features of the AD5379 are used, then the
output range required is slightly different. The output range
chosen should take into account the offset and gain errors that
need to be trimmed out. Therefore, the chosen output range
should be larger than the actual required range.
The reference levels required can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT
including the maximum offset and gain errors expected.
4.
Choose the new VOUT
max
and VOUT
min
required, keeping
the new VOUT limits centered on the nominal values and
assuming REFGND is zero (or equal to AGND). Note that
V
DD
and V
SS
must provide sufficient headroom.
5.
Calculate the values of V
REF
(+) and V
REF
() as follows:
V
REF
(+)
min
= (
VOUT
max
VOUT
min
)/3.5
V
REF
()
max
= (
AGND
+
VOUT
min
)/2.5
In addition, when using reference values other than those
suggested (V
REF
(+) = 5 V and V
REF
() = 3.5 V), the expected
offset error component changes as follows:
V
OFFSET
= 0.125 × (
V
REF
()
A
+ 0.7 ×
V
REF
(+)
A
)
where:
V
REF
()
A
is the new negative reference value.
V
REF
(+)
A
is the new positive reference value.
If this offset error too large to calibrated out, then it is possible
to adjust the negative reference value to account for this using
the following equation:
V
REF
()
NEW
=
V
REF
()
A
V
OFFSET
/2.625
Reference Selection Example
Nominal Output Range
= 10 V; (2 V to +8 V)
Offset Error
= ±100 mV;
Gain Error
= ±3%;
REFGND = AGND =
0 V;
1)
Gain Error
= ±3%;
=> Maximum Positive Gain Error
= +3%
=> Output Range incl. Gain Error
= 10 + 0.03 (10) = 10.3 V
2) Offset Error
= ±100 mV;
=> Maximum Offset Error Span
= 2(100) mV = 0.2 V
=> Output Range incl. Gain Error and Offset Error
=
10.3 + 0.2 = 10.5 V
3) V
REF
(+) and V
REF
() Calculation:
Actual Output Range =
10.5 V, that is, 2.25 V to +8.25 V
(centered);
=>
V
REF
(+) = (8.25 + 2.25)/3.5 = 3 V
V
REF
() = 2.25/2.5 = 0.9 V
If the solution yields inconvenient reference levels, the user can
adopt one of three approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select convenient reference levels above V
REF
(+)
min
or below
V
REF
()
max
. Modify the gain and offset registers to downsize
the references digitally. In this way, the user can use almost
any convenient reference level, but may reduce perform-
ance by overcompaction of the transfer function.
Use a combination of these two approaches.
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