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| 型號(hào)： | AD5347BCP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | Dual 12-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁(yè)數(shù)： | 18/24頁(yè) |
| 文件大小： | 949K |
| 代理商： | AD5347BCP-REEL7 |
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AD5346/AD5347/AD5348
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 s for V
DD
= 5 V and 5 μs when V
DD
=
3 V. This is the time from a rising edge on the PD pin to when
the output voltage deviates from its power-down voltage. See
Figure 31.
Rev. 0 | Page 18 of 24
SUGGESTED DATA BUS FORMATS
In many applications, the GAIN and BUF pins are hardwired.
However, if more flexibility is required, they can be included in
a data bus. This enables the user to software program GAIN,
giving the option of doubling the resolution in the lower half of
the DAC range. In a bused system, GAIN and BUF may be
treated as data inputs because they are written to the device
during a write operation and take effect when LDAC is taken
low. This means that the reference buffers and the output
amplifier gain of multiple DAC devices can be controlled using
common GAIN and BUF lines. Note that GAIN and BUF are
not read back during an RD operation.
Table 8. AD5346/AD5347/AD5348 Truth Table
CLR
LDAC
1
1
1
1
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
0
X
X
X = Don’t Care
The AD5347 and AD5348 data bus must be at least 10 and 12
bits wide, respectively, and are best suited to a 16-bit data bus
system.
Examples of data formats for putting GAIN and BUF on a
16-bit data bus are shown in Figure 40. Note that any unused
bits above the actual DAC data may be used for GAIN and BUF.
0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
GAIN
X
X
BUF
X
X = UNUSED BIT
X
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
GAIN
X
X
BUF
DB11 DB10
AD5347
AD5348
Figure 40. AD5347/AD5348 Data Format for Word Load with
GAIN and BUF Data on 16-Bit Bus
CS
1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
WR
X
1
X
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
1
1
1
1
1
1
1
1
X
0
RD
X
1
X
1
1
1
1
1
1
1
1
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
0
A2
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
A1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
A0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
Function
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Input Register
Load DAC B Input Register
Load DAC C Input Register
Load DAC D Input Register
Load DAC E Input Register
Load DAC F Input Register
Load DAC G Input Register
Load DAC H Input Register
Read Back DAC Register A
Read Back DAC Register B
Read Back DAC Register C
Read Back DAC Register D
Read Back DAC Register E
Read Back DAC Register F
Read Back DAC Register G
Read Back DAC Register H
Update DAC Registers
Invalid Operation
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| AD5347BRU | Dual 12-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
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| AD5348 | Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85 |
| AD5348BCP | Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85 |
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