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| 型號： | AD5348 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85 |
| 中文描述： | 2.5 V至5.5 V，并行接口2.5 V至5.5 V，并行接口 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 949K |
| 代理商： | AD5348 |
2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
FEATURES
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to V
REF
or 0 V to 2 × V
REF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR
facility
Readback
Buffered/unbuffered reference inputs
20 ns WR
time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
APPLICATIONS
Rev.
0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Tel: 781.329.4700Fax: 781.326.8703
www.analog.comPortable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5346/AD5347/AD5348
1
are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to V
REF
or 0 V to 2 × V
REF
.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
DGND
V
DD
AGND
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
STRING
DAC A
STRING
DAC B
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
G
V
OUT
H
V
OUT
F
POWER-ON
RESET
V
OUT
A
V
REF
EF
V
REF
AB
PD
INTER-
FACE
LOGIC
GAIN
DB11
DB0
CS
WR
A0
A1
CLR
LDAC
.
.
BUF
A2
RD
V
REF
GH
V
REF
CD
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
AD5348
POWER-DOWN
LOGIC
0
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
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| AD5348BCP | Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85 |
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