參數(shù)資料
型號(hào): AD5317
廠商: Analog Devices, Inc.
英文描述: Dual Rail-To-Rail,Voltage Output 10-Bit DACs(滿幅度電壓輸出雙10位D/A轉(zhuǎn)換器)
中文描述: 雙通道軌至軌電壓輸出10位DAC(滿幅度電壓輸出雙10位的D / A轉(zhuǎn)換器)
文件頁(yè)數(shù): 7/8頁(yè)
文件大小: 336K
代理商: AD5317
2
7
AD5307/17 Prelim Technical Information
Prelim A1 4/98
in temperature. It is expressed in μV/°C.
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. Code plot can be seen in Figure x.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. A typical DNL vs. Code plot can be seen in Fig-
ure x.
FULL-SCALE ERROR
Full-scale error is a measure of the output error when full-scale
code (all ones) is loaded to the DAC register. Ideally the output
should be V
DD
- 1LSB. Full-scale error is expressed in LSBs. A
plot of Full-scale error vs. Temperature can be seen in Figure x.
ZERO-CODE ERROR
Zero-code error is a measure of the output error when zero-code
(all zeroes) is loaded to the DAC register. Ideally the output
should be 0V. The zero-code error is always positive in the
AD5307/17 because the outputs of the DACs cannot go below
0V. It is due to a combination of the offset errors in the DACs
and output amplifiers. Zero-code error is expressed in LSBs. A
plot of Zero-code error vs. Temperature can be seen in Figure x.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal ex-
pressed as a percent of the full-scale range.
TOTAL UNADJUSTED ERROR
Total Unadjusted Error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE vs.
Code plot can be seen in Figure x.
ZERO-CODE ERROR DRIFT
This is a measure of the change in zero-code error with a change
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DIGITAL-TO-ANALOG GLITCH IMPULSE
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-secs
and is measured when the digital input code is changed by 1LSB
at the major carry transition.
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC but
is measured when the DAC output is not updated. It is specified
in nV-secs and is measured with a full-scale change on the digital
input pins, i.e. from all 0s to all 1s and vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change (but not output change) of the other
DAC. It is measured by loading one of the input registers with a
full-scale code change (all 0s to all 1s and vice versa) while keep-
ing
LDAC
high and monitoring the output of the other DAC.
The area of the glitch is expressed in nV-secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping
LDAC
high. Then
pulse
LDAC
low and monitor the output of the DAC whose digi-
tal code was not changed. The area of the glitch is expressed in
nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. It is measured by loading one of the DACs with
a full-scale code change (all 0s to all 1s and vice versa) while
keeping
LDAC
low and monitoring the output of the other
DAC. The area of the glitch is expressed in nV-secs.
DC CROSSTALK
This is the DC change in the output level of one DAC in re-
sponse to a change in the output of the other DAC. It is mea-
sured with a full-scale output change on one DAC while
monitoring the other DAC. It is expressed in
μ
V.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is expressed in % of change in out-
put voltage per % of change in V
DD
for full-scale output of the
DAC. V
DD
is varied
±
10 %.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being up-
dated (i.e.
LDAC
is high). It is expressed in dBs.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its recon-
structed version using the DAC. The sine wave is used as the ref-
erence for the DAC and the THD is a measure of the harmonics
present on the DAC output.It is measured in dBs.
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3dB below the input.
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dBs.
相關(guān)PDF資料
PDF描述
AD5320(中文) Rail-to-Rail Voltage Output 12-Bit DAC(滿幅度電壓輸出12位D/A轉(zhuǎn)換器)
AD5346 Dual 12-bit 80MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
AD5346BCP Dual 12-bit 80MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
AD5346BCP-REEL7 Dual 12-bit 105MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
AD5346BRU Dual 12-bit 105MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5317ARU 功能描述:IC DAC 10BIT QUAD W/BUFF 16TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散(最大):- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率(每秒):*
AD5317ARU-REEL7 功能描述:IC DAC 10BIT QUAD W/BUFF 16TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散(最大):- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率(每秒):*
AD5317ARUZ 功能描述:IC DAC 10BIT QUAD W/BUFF 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散(最大):- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP,8-MSOP(0.118",3.00mm 寬) 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓,單極 采樣率(每秒):* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF)
AD5317ARUZ-REEL7 功能描述:IC DAC 10BIT QUAD W/BUFF 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?,串行,SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散(最大):2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP(4x3) 包裝:管件 輸出數(shù)目和類型:8 電壓,單極 采樣率(每秒):*
AD5317BRU 功能描述:IC DAC 10BIT QUAD W/BUFF 16TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散(最大):55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流,單極;1 電流,雙極 采樣率(每秒):*