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參數(shù)資料
| 型號： | AD5300BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 8-BIT DAC, PDSO6 |
| 封裝： | SOT-23, 6 PIN |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 180K |
| 代理商： | AD5300BRT |
AD5300
–9–
REV. A
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
Figure 24. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s for
V
DD
= 3 V. See Figure 18 for a plot.
MICROPROCESSOR INTERFACING
AD5300 to ADSP-2101/ADSP-2103 Interface
Figure 25 shows a serial interface between the AD5300 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT Transmit Alternate Framing
Mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: Internal Clock Operation, Active Low Framing, 16-
Bit Word Length. Transmission is initiated by writing a word to
the Tx register after the SPORT has been enabled.
ADSP-2101/
ADSP-2103*
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
SCLK
AD5300*
TFS
SCLK
Figure 25.AD5300 to ADSP-2101/ADSP-2103 Interface
DB15
DB0
SCLK
SYNC
DIN
DB15
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
INVALID WRITE SEQUENCE:
SYNC
HIGH BEFORE 16
TH
FALLING EDGE
Figure 23.
SYNC
Interrupt Facility
SYNC
Interrupt
In a normal write sequence, the
SYNC
line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if
SYNC
is brought high before the
16th falling edge this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 23.
Power-On-Reset
The AD5300 contains a power-on-reset circuit which controls
the output voltage during power-up. The DAC register is filled
with zeros and the output voltage is 0 V. It remains there until
a valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the out-
put of the DAC while it is in the process of powering up.
Power-Down Modes
The AD5300 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB13
and DB12) in the control register. Table I shows how the state
of the bits corresponds to the mode of operation of the device.
Table I. Modes of Operation for the AD5300
DB13
DB12
Operating Mode
0
0
Normal Operation
Power-Down Modes
1 k
to GND
100 k
to GND
Three-State
0
1
1
1
0
1
When both bits are set to 0, the part works normally with its
normal power consumption of 140
μ
A at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different options.
The output is connected internally to GND through a 1 k
resis-
tor, a 100 k
resistor or it is left open-circuited (Three-State).
The output stage is illustrated in Figure 24.
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