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參數(shù)資料
| 型號(hào)： | AD5300BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 8-BIT DAC, PDSO6 |
| 封裝： | SOT-23, 6 PIN |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | AD5300BRT |
AD5300
–4–
REV. A
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
OUT
GND
V
DD
SYNC
SCLK
DIN
AD5300
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
NC
AD5300
SYNC
V
OUT
GND
V
DD
SCLK
DIN
NC
NC = NO CONNECT
SOT-23
m
SOIC
PIN FUNCTION DESCRIPTIONS
SOT-23 Pin Numbers
Pin
No.
Mnemonic
Function
1
2
3
V
OUT
GND
V
DD
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and V
DD
should be de-
coupled to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level triggered control input (active low). This is the frame synchronization signal for the input
data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the fall-
ing edges of the following clocks. The DAC is updated following the 16th clock cycle unless
SYNC
is taken high before this edge in which case the rising edge of
SYNC
acts as an interrupt and the
write sequence is ignored by the DAC.
4
DIN
5
SCLK
6
SYNC
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