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參數(shù)資料
| 型號： | AD5227BUJZ100-RL72 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 64-Position Up/Down Control Digital Potentiometer |
| 中文描述： | 64工位上/下控制數(shù)字電位器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 331K |
| 代理商： | AD5227BUJZ100-RL72 |
AD5227
Parameter
INTERFACE TIMING CHARACTERISTICS (applies to all parts
6, 10
)
Clock Frequency
Input Clock Pulse Width
CS to CLK Setup Time
CS Rise to CLK Hold Time
U/D to Clock Fall Setup Time
Rev. 0 | Page 4 of 16
Symbol
Conditions
Clock level high or low
Min
10
10
10
10
Typ
1
Max
Unit
MHz
ns
ns
ns
ns
f
CLK
t
CH
, t
CL
t
CSS
t
CSH
t
UDS
50
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
NL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= V.
10
All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
V
DD
= 5 V.
INTERFACE TIMING DIAGRAMS
0
CS = LOW
U/D = HIGH
CLK
R
WB
Figure 2. Increment R
WB
0
CS = LOW
U/D = 0
CLK
R
WB
Figure 3. Decrement R
WB
0
1
0
1
0
1
0
CS
CLK
U/D
R
WB
t
S
t
UDS
t
CL
t
CH
t
CSS
t
CSH
Figure 4. Detailed Timing Diagram(Only R
WB
Decrement Shown)
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相關代理商/技術參數(shù) |
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|---|---|
| AD5227BUJZ10-R2 | 功能描述:IC DGTL POT 10K UP/DN TSOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標準包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標準值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應商設備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
| AD5227BUJZ10-R22 | 制造商:AD 制造商全稱:Analog Devices 功能描述:64-Position Up/Down Control Digital Potentiometer |
| AD5227BUJZ10-RL7 | 功能描述:IC DGTL POT UP/DN 10K TSOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| AD5227BUJZ10-RL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:64-Position Up/Down Control Digital Potentiometer |
| AD5227BUJZ50 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 64POS 50KOHM SGL 8PIN TSOT - Bulk |
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