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參數(shù)資料
| 型號： | AD1893JSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SAMPLE-RATE CONV 16BIT 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | SamplePort™ |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 多媒體 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
AD1893
REV. A
–7–
THEORY OF OPERATION
There are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1893 SamplePort does not require
understanding either model. This section is included for those
who wish a deeper understanding of its operation.
Interpolation/Decimation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRATIO) by inserting IRATIO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). The frequency domain charac-
teristics of the input signal are unaltered by this operation, ex-
cept that the zero-padded sequence is considered to be sampled
at a frequency which is the product of original sampling fre-
quency multiplied by IRATIO.
The zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. The inter-
polated output signal has been quantized to a much finer time
scale than the original sequence. The interpolated sequence is
INPUT
SIGNAL
OUTPUT
SIGNAL
ZERO STUFF
INTERPOLATION
FIR LOW-
PASS
FILTER
ZERO ORDER
HOLD
REGISTER
RESAMPLING
DECIMATION
A
BC
DE
B
C
D
E
A
TIME
AMP
Figure 1. Interpolation/Decimation Model—Time Domain View
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). This resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. The output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. There is always some error in the output
sample amplitude due to the fact that the output sampling switch
does not close at a time that exactly corresponds to a point on the
fine time scale of the interpolated sequence. However, this error
can be made arbitrarily small by using a very large interpolation
ratio. The AD1893 SamplePort ASRC uses an equivalent IRATIO
of 65,536 to provide 16-bit accuracy (
≈–96 dB THD+N) across
the 0 kHz to 20 kHz audio band.
The number of FIR filter taps and associated coefficients is
approximately 4 million. The equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1893 ASRC to reduce
the complexity and throughput requirements of the hardware
implied by this interpolation/decimation model.
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| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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