- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10218 > AD1893JSTZRL (Analog Devices Inc)IC SAMPLE-RATE CONV 16BIT 44TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD1893JSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SAMPLE-RATE CONV 16BIT 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | SamplePort™ |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 多媒體 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
AD1893
–4–
REV. A
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
limited to avoid alias distortion on the output signal. The
AD1893 dynamically alters the low-pass filter cutoff frequency
smoothly and slowly, so that real-time variations in the sample
rate ratio are possible without degradation of the audio quality.
The AD1893 has a pin selectable slow- or fast-settling mode.
This mode determines how quickly the ASRC adapts to a
change in either the input sample clock frequency (FSIN) or the
output sample clock frequency (FSOUT). In the slow-settling
mode, the control loop which computes the ratio between FSIN
and FSOUT settles in approximately 800 ms and begins to reject
jitter above 3 Hz. The slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. The fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrowband noise modulation products on the
output signal.
The AD1893 features short group delay processing. This feature
relates to the depth of the First-In, First-Out (FIFO) memory,
which buffers the input data samples before they are processed
by the FIR convolver. In the AD1893, the group delay is
approximately 700
s. If the read and write pointers that
manage the FIFO cross (indicating underflow or overflow), the
AD1893 asserts the mute output (MUTE_O) pin HI for 128
output clock cycles. If MUTE_O is connected to the mute input
(MUTE_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
The AD1893 includes an on-chip oscillator that only requires
the user provide an external crystal. By removing the need for
an external oscillator, the AD1893 lowers the total cost of own-
ership to the end user. The AD1893 also includes a power-
down mode, which is invoked with the PWRDWN pin.
Asserting this control signal HI will place the AD1893 into a
very low power dissipation in active and standby condition.
The AD1893 is fabricated in a 0.8
m single poly, double metal
CMOS process and are packaged in a 0.6" wide 28-lead plastic
DIP and a 10 mm by 10 mm body size 44-lead LQFP. The
AD1893 operates from a +3 V to +5 V power supply over the
temperature range of 0
°C to +70°C.
DEFINITIONS
Dynamic Range
The ratio of a near full-scale input signal to the integrated noise
in the passband (0 kHz to
≈20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the values
of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Group Delay
Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian
phase with respect to radian frequency at a given frequency.
Transport Delay
The time interval between when an impulse is applied to the
converter’s input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). Transport delay is
independent of frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP3238EEA-L/TR | IC TXRX RS232 INTELLIGENT 28SSOP |
| CS3308-CQZR | IC ANLG VOL CTRL 8CH 48-LQFP |
| VI-J1K-MX-S | CONVERTER MOD DC/DC 40V 75W |
| VE-21J-IU-F4 | CONVERTER MOD DC/DC 36V 200W |
| SP3243EUER-L/TR | IC TXRX RS232 INTELLIGENT 32QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895 | 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter |
| AD1895AYRS | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER |
| AD1895AYRSRL | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP T/R |
| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。