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參數(shù)資料
| 型號： | AAT2120IES-0.6-T1 |
| 廠商： | Advanced Analogic Technologies, Inc. |
| 英文描述： | 500mA Low Noise Step-Down Converter |
| 中文描述： | 低噪聲500mA的降壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 1145K |
| 代理商： | AAT2120IES-0.6-T1 |
AAT2120
500mA Low Noise Step-Down Converter
14
2120.2007.10.1.1
Figure 2: AAT2120 Evaluation Board
Top Side Layout.
Figure 3: Exploded View of AAT2120
Evaluation Board Top Side Layout.
Figure 4: AAT2120 Evaluation Board
Bottom Side Layout.
Layout
The suggested PCB layout for the AAT2120 in an
STDFN22-8 package is shown in Figures 2, 3, and 4.
The following guidelines should be used to help
ensure a proper layout.
1. The input capacitor (C1) should connect as
closely as possible to VP (Pin 1), PGND (Pin 8),
and GND (Pin 3)
2. C2 and L1 should be connected as closely as pos-
sible. The connection of L1 to the LX pin (Pin 7)
should be as short as possible. Do not make the
node small by using narrow trace. The trace
should be kept wide, direct and short.
3. The feedback pin (Pin 4) should be separate
from any power trace and connect as closely as
possible to the load point. Sensing along a
high-current load trace will degrade DC load
regulation. Feedback resistors should be
placed as closely as possible to the FB pin (Pin
4) to minimize the length of the high imped-
ance feedback trace. If possible, they should
also be placed away from the LX (switching
node) and inductor to improve noise immunity.
4. The resistance of the trace from the load return
to PGND (Pin 8) and GND (Pin 3) should be
kept to a minimum. This will help to minimize
any error in DC regulation due to differences in
the potential of the internal signal ground and
the power ground.
5. A high density, small footprint layout can be
achieved using an inexpensive, miniature, non-
shielded, high DCR inductor.
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