參數(shù)資料
型號(hào)： A8351601
廠商： AMIC Technology Corporation
英文描述： Bar Code Reader
中文描述： 條碼閱讀器
文件頁數(shù)： 12/44頁
文件大小： 439K
代理商： A8351601
A8351601 Series
(July, 2002, Version 1.0)
11
AMIC Technology, Inc.
T2CON: (continued)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/
T2
CP/
RL2
Register Description:
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
Software START/STOP control for Timer 2. A logic 1 starts the Timer.
Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling
edge).
Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2
=1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions
at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the Timer
is forced to auto-reload on Timer 2 overflow.
TR2
C/
T2
T2CON.2
T2CON.1
CP/
RL2
T2CON.0
Notes:
Timer 2 Operating Modes
RCLK + TCLK
CP/
RL2
0
0
1
TR2
1
1
1
MODE
0
1
X
16-Bit Auto-Reload
16-Bit Capture
Baud Rate Generator
ADD(A1H):
Extra Additional Register. Not Bit Addressable.
7
-
6
-
5
4
3
2
1
DF
0
Delay2
Delay1
Delay0
T2EXREV
RAMDIS
Register Description:
-
-
D2
D1
D0
T2EXREV
DF
RAMDIS
Not implemented, reserve for future use.
Not implemented, reserve for future use.
PWM3 delay control bit.
PWM3 delay control bit.
PWM3 delay control bit.
T2EX reverse control bit. Set/Cleared by software specify T2EX pin reverse/no reverse.
Double system frequency control bit. Set/Cleared by software specify Xtal frequency *2 / Xtal frequency.
Build in 8K bytes SRAM enable/disable control bit. Set/Cleared by software specify
Enable/disable build in 8K bytes SRAM.
Bit <5:3>
Delay
0
1
2
3
4
5
6
7
4 CLK
5 CLK
6 CLK
7 CLK
8 CLK
9 CLK
10 CLK
11 CLK
(D2, D1, D0) controlled the delay time of PWM3 after PWM1 change.
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