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參數(shù)資料
| 型號： | A67P9336E-3.5 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| 中文描述： | 100萬X 18，為512k × 36 LVTTL，流水線ZeBL的SRAM |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 249K |
| 代理商： | A67P9336E-3.5 |
A67P0618/A67P9336 Series
Preliminary
1M X 18, 512K X 36 LVTTL, Pipelined ZeBL
TM
SRAM
PRELIMINARY (September, 2004, Version 0.0)
2
AMIC Technology, Corp.
Features
Fast access time:
2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
Zero Bus Latency between READ and WRITE cycles
allows 100% bus utilization
Signal +2.5V
±
5% power supply
Individual Byte Write control capability
Clock enable (
CEN
) pin to enable clock and suspend
operations
Clock-controlled and registered address, data and
control signals
Registered output for pipelined applications
Three separate chip enables allow wide range of
options for CE control, address pipelining
Internally self-timed write cycle
Selectable BURST mode (Linear or Interleaved)
SLEEP mode (ZZ pin) provided
Available in 100 pin LQFP package
General Description
The AMIC Zero Bus Latency (ZeBL
TM
) SRAM family
employs high-speed, low-power CMOS designs using an
advanced CMOS process.
The A67P0618, A67P9336 SRAMs integrate a 1M X 18,
512K X 36 SRAM core with advanced synchronous
peripheral circuitry and a 2-bit burst counter. These SRAMs
are optimized for 100 percent bus utilization without the
insertion of any wait cycles during Write-Read alternation.
The positive edge triggered single clock input (CLK) controls
all synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs,
active low chip enable (
CE
), two additional chip enables for
easy depth expansion (CE2,
CE2
), cycle start input
(ADV/
LD
), synchronous clock enable (
CEN
), byte write
enables (
BW1
,
BW2
,
BW3
,
BW4
) and read/write (R/
W
).
Asynchronous inputs include the output enable (
OE
), clock
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/
LD
) pin in Low
state. Subsequent burst address can be internally
generated by the chip and controlled by the same input pin
ADV/
LD
in High state.
Write cycles are internally self-time and synchronous with
the rising edge of the clock input and when R/
W
is Low.
The feature simplified the write interface. Individual Byte
enables allow individual bytes to be written.
BW1
controls
I/Oa pins;
BW2
controls I/Ob pins;
BW3
controls I/Oc pins;
and
BW4
controls I/Od pins. Cycle types can only be
defined when an address is loaded.
The SRAM operates from a +2.5V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A67P9336E-3.8 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A67P9336E-4.2 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A67P9336E-2.6 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A6801 | DABiC-5 Latched Sink Drivers |
| A6801SA | DABiC-5 Latched Sink Drivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67P9336E-4.2 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A67S | 制造商:M/A-COM Technology Solutions 功能描述:GAIN BLOCK |
| A6800 | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-5 Latched Sink Drivers |
| A6800SA-T | 功能描述:IC SINK DRIVER LATCHED 14-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 內(nèi)部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:高端/低端驅(qū)動器 輸入類型:SPI 輸出數(shù):8 導(dǎo)通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A6800SA-T | 制造商:Allegro MicroSystems 功能描述:Driver IC Number of Drivers:4 |
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