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參數(shù)資料
| 型號： | A67P9336E-3.2 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| 中文描述： | 100萬X 18，為512k × 36 LVTTL，流水線ZeBL的SRAM |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 249K |
| 代理商： | A67P9336E-3.2 |
A67P0618/A67P9336 Series
PRELIMINARY (September, 2004, Version 0.0)
8
AMIC Technology, Corp.
Truth Table (Notes 5 - 7)
Operation
Address
Used
None
CE
H
CE2
X
CE2
ZZ
ADV/
LD
L
R/
W
BWx
X
OE
CEN
L
CLK
I/O
Notes
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Continue Deselect
Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/Dummy READ
(Begin Burst)
Dummy READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE Abort
(Begin Burst)
WRITE Abort
(Continue Burst)
IGNORE Clock Edge
(Stall)
SLEEP Mode
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock
Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
BWx
= H means all byte write signals (
BW1
,
BW2
,
BW3
and
BW4
) are HIGH.
BWx
= L means one or more byte write signals are LOW.
6.
BW1
enables WRITEs to Byte “a” (I/Oa pins);
BW2
enables WRITEs to Byte “b” (I/Ob pins);
BW3
enables WRITEs to
Byte “c” (I/Oc pins);
BW4
enables WRITEs to Byte “d” (I/Od pins).
7. The address counter is incremented for all Continue Burst cycles.
X
L
X
X
L
→
H
High-Z
None
X
H
X
L
L
X
X
X
L
L
→
H
High-Z
None
X
X
L
L
L
X
X
X
L
L
→
H
High-Z
None
X
X
X
L
H
X
X
X
L
L
→
H
High-Z
1
External
L
L
H
L
L
H
X
L
L
L
→
H
Q
Next
X
X
X
L
H
X
X
L
L
L
→
H
Q
1,7
External
L
L
H
L
L
H
X
H
L
L
→
H
High-Z
2
Next
X
X
X
L
H
X
X
H
L
L
→
H
High-Z
1,2,7
External
L
L
H
L
L
L
L
X
L
L
→
H
D
3
Next
X
X
X
L
H
X
L
X
L
L
→
H
D
1,3,7
None
L
L
H
L
L
L
H
X
L
L
→
H
High-Z
2,3
Next
X
X
X
L
H
X
H
X
L
L
→
H
High-Z
1,2,3,7
Current
X
X
X
L
X
X
X
X
H
L
→
H
-
4
None
X
X
X
H
X
X
X
X
X
X
High-Z
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| A67P0618E-2.6 | CAT5E 350 MHZ PATCH CORD 5FT, WHITE, 25-PACK |
| A67P0618 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
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