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Table 1: Pin Description
A49LF040A
PRELIMINARY (March, 2006, Version 0.1)
4
AMIC Technology, Corp.
Notes: IN=Input, OUT=output, I/O=Input/Output, PWR=Power
Interface
A/A
Mux
Symbol
Pin Name
Type
LPC
Descriptions
A
10
-A
0
Address
IN
X
Inputs for addresses during Read and Write operations in A/A Mux
mode. Row and column addresses are latched by
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE is high.
To control the data output buffers.
To control the Write operations.
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, LPC mode is enabled.
This pin must be setup at power-up or before return from reset and
not change during device operation. This pin is internally pulled
down with a resistor between 20-100 K
This is the second reset pin for in-system use.
INIT
and RST
pins are internally combined and initialize a device reset when
driven low.
These four pins are part of the mechanism that allows multiple
LPC devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count strapping.
These pins are internally pulled down with a resistor between 20-
100 K
.
These individual inputs can be used for additional board flexibility.
The state of these pins can be read immediately at boot, through
LPC internal registers. These inputs should be at their desired
state before the start of the PCI clock cycle during which the read
is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
To prevent any write operations to the Boot Block when driven low,
regardless of the state of the block lock registers. When TBL is
high it disables hardware write protection for the top Boot Block.
This pin cannot be left unconnected.
I/O Communications in LPC mode.
To provide a clock input to the device. This pin is the same as that
for the PCI clock and adheres to the PCI specifications.
To indicate start of a data transfer operation. LFRAME is also
used to abort an LPC cycle in progress.
To reset the operation of the device
When low, prevents any write operations to all but the highest
addressable block. When WP is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
This pin is used to determine if the device is busy in write
operations. Valid only in A/A Mux mode.
Reserved. These pins must be left unconnected.
To provide power supply (3.0-3.6Volt).
Circuit ground. All VSS pins must be grounded.
Unconnected pins.
C
R/
pin.
I/O
7
-I/O
0
Data
I/O
X
OE
WE
Output Enable
Write Enable
IN
IN
X
X
MODE
Interface Mode
Select
IN
X
X
INIT
Initialize
IN
X
ID[3:0]
Identification Inputs
IN
X
GPI[4:0]
General Purpose
Inputs
IN
X
TBL
Top Block Lock
IN
X
LAD[3:0]
LPC Interface I/Os
I/O
X
LCLK
Clock
IN
X
LFRAME
Frame
IN
X
RST
Reset
IN
X
X
WP
Write Protect
IN
X
C
R/
Row/Column Select
IN
X
B
R/
Ready/Busy
OUT
X
RES
VDD
VSS
NC
Reserved
Power Supply
Ground
No Connection
X
X
X
X
PWR
PWR
X
X
X