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Preliminary
Current State Bank n - Command to Bank m (Different bank) (continued)
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
29
AMIC Technology, Corp.
Current State
CS
RAS
CAS
WE
Command
Action
Note
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
H
L
L
H
H
L
L
Active
Read
Write
Precharge
Active
Read
Write
Precharge
Select and Activate Row
Select column and start new Read Burst
Select column and start Write Burst
Select and Activate Row
Select column and start Read Burst
Select column and start new Write Burst
1-6
1-7, 10
1-7, 9, 10
1-6
1-6
1-7, 10
1-7, 10
1-6
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
XSNR
/ t
XSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active:
A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and no register accesses
are in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled:
See note 10.
Write with Auto Precharge Enabled:
See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was
executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of
the data in the burst. For Write with Auto Precharge, the precharge period begins when t
WR
ends, with t
WR
measured as if Auto
Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t
RP
)
begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states,
Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and
Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention
between Read data and Write data must be avoided).