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Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
18
AMIC Technology, Corp.
Operating Mode
The normal operating mode is selected by issuing a Mode
Register Set Command with bits A7-A11 to zero, and bits
A0-A6 set to the desired values. A DLL reset is initiated by
issuing a Mode Register Set command with bits A7 and
A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set
to the desired values. A Mode Register Set command issued
to reset the DLL should always be followed by a Mode
Register Set command to select normal operating mode.
All other combinations of values for A7-A11 are reserved for
future use and/or test modes. Test modes and reserved
states should not be used as unknown operation or
incompatibility with future versions may result.
Extended Mode Register
The Extended Mode Register controls functions beyond those
controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength
selection, bit A1; and
QFC
output enable/disable, bit A2
(NTC optional). These functions are controlled via the bit
settings shown in the Extended Mode Register Definition. The
Extended Mode Register is programmed via the Mode
Register Set command (with BA0 = 1 and BA1 = 0) and
retains the stored information until it is programmed again or
the device loses power. The Extended Mode Register must
be loaded when all banks are idle, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements result in
unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is
required during power up initialization, and upon returning to
normal operation after having disabled the DLL for the
purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is
automatically re-enabled upon exit of self refresh operation.
Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal
clock to lock to the externally applied clock before a Read
command can be issued. This is the reason for introducing
timing parameter t
XSRD
for DDR SDRAM’s (Exit Self Refresh
to Read Command).
Non- Read commands can be issued 2 clocks after the DLL is
enabled via the EMRS command (t
MRD
) or 10 clocks after the
DLL is enabled via self refresh exit command (t
XSNR
, Exit Self
Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be
SSTL_2, Class II.
CAS
Enable/Disable
The
QFC
signal is an optional DRAM output control used to
isolate module loads (DIMMs) from the system memory bus
by means of external FET switches when the given module
(DIMM) is not being accessed. The
QFC
function is an
optional feature for NANYA and is not included on all DDR
SDRAM devices.
Extended Mode Register Definition
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*
1*
Operating Mode
CAS
DS
DLL
Operating Mode
CAS
Drive Strength
DLL
A11-A3
0
A2-A0
Valid
Type
A2
0
Type
Disable
A1
0
Type
Normal
A0
0
Type
Enable
Normal Operation
-
-
All Other States
Reserved
1
Enable
(Optional)
1
Reserved
1
Disable
Note:
*
BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)