參數(shù)資料
型號(hào): A43E16161V-75UF
廠商: AMIC Technology Corporation
英文描述: 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM
中文描述: 100萬(wàn)× 16位× 2銀行低功耗同步DRAM
文件頁(yè)數(shù): 34/46頁(yè)
文件大?。?/td> 1314K
代理商: A43E16161V-75UF
A43E16161
PRELIMINARY (August, 2005, Version 0.0)
33
AMIC Technology, Corp.
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Burst Length = Full Page)
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
RAa
WE
DQM
DAa4
DAa3
DAa1
DAa2
DAb0
DAb1
DAb2
DAb3
DQ
Precharge
(A-Bank)
Write
(A-Bank)
CAb
Write
(A-Bank)
Burst Stop
* Note 1
* Note 1
* Note 2
DAa0
DAb4
DAb5
t
RDL
t
BDL
* Note 3
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
4. Burst stop is valid only at every burst length.
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