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參數(shù)資料
| 型號(hào)： | A43E06321G-75UF |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| 中文描述： | 為512k × 32位× 2銀行低功耗同步DRAM |
| 文件頁(yè)數(shù)： | 9/46頁(yè) |
| 文件大?。?/td> | 1351K |
| 代理商： | A43E06321G-75UF |
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A43E06321
PRELIMINARY
(July, 2005, Version 0.0)
8
AMIC Technology, Corp.
Simplified Truth Table
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA A10
/AP
A9~A0
Notes
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Extended Mode Register Set
H
X
L
L
L
L
L
OP CODE
1,2
Auto Refresh
H
L
3
Entry
H
L
L
L
H
X
X
3
L
H
H
H
3
Refresh
Self
Refresh
Exit
L
H
H
L
X
L
X
H
X
H
X
X
3
4
Bank Active & Row Addr.
H
X
X
V
Row Addr.
Auto Precharge Disable
L
H
L
H
4
4,5
4
4,5
6
7
8
Read &
Column Addr. Auto Precharge Enable
Auto Precharge Disable
Write &
Column Addr. Auto Precharge Enable
Burst Stop
Bank Selection
Precharge
Both Banks
H
X
L
H
L
H
X
V
Column
Addr.
H
X
L
H
L
L
X
V
Column
Addr.
H
X
L
H
H
L
X
X
V
X
L
H
H
X
L
L
H
L
X
X
L
H
X
L
H
L
H
H
X
X
H
X
V
X
X
H
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
H
V
X
L
H
L
X
H
X
H
X
H
X
L
X
No Operation Command
H
X
X
X
Deep Power Down Entry
Deep Power Down Exit
Note :
1. OP Code: Operand Code
A0~A10, BA: Program keys. (@MRS, EMRS)
2. MRS can be issued only when all banks are at precharge state.
A new command can be issued after 2 clock cycle of MRS, EMRS.
3. Auto refresh functions is same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks are at precharge state.
4. BA: Bank select address.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued at every burst length.
6. Bust stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
8. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.
H
L
L
H
X
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
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PDF描述 |
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| A43E06321G-95F | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321 | Knob, Accessories; Color:Red; External Height:0.27" RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06321G-95F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E0632G-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0632G-95I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0632V-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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