Revision 11 2-21 Table 2-25 Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode In" />
參數(shù)資料
型號: A3PN250-ZVQG100I
廠商: Microsemi SoC
文件頁數(shù): 44/114頁
文件大?。?/td> 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: ProASIC3 nano
RAM 位總計(jì): 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
ProASIC3 nano Flash FPGAs
Revision 11
2-21
Table 2-25 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
Table 2-26 I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
(Schmitt
trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS
(Schmitt
trigger
enabled)
No requirement
No requirement, but input
noise voltage cannot exceed
Schmitt hysteresis
20 years (100°C)
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Microsemi recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
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