5-2 Revision 11 Revision 9 (continued) The reference to guidelines for global spines and VersaTile rows, given in the "" />
參數(shù)資料
型號: A3PN250-ZVQG100I
廠商: Microsemi SoC
文件頁數(shù): 11/114頁
文件大小: 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標準包裝: 90
系列: ProASIC3 nano
RAM 位總計: 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
Datasheet Information
5-2
Revision 11
Revision 9
(continued)
The reference to guidelines for global spines and VersaTile rows, given in the "Global
he "Spine Architecture"
section of the Global Resources chapter in the IProASIC3 nano FPGA Fabric
(SAR 34736).
Figure 2-3 has been modified for the DIN waveform; the Rise and Fall time label has
been changed to tDIN (37114).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
tables were revised for clarification. They now state that the minimum drive strength
for the default software configuration when run in wide range is ±100 A. The drive
strength displayed in software is supported in normal range only. For a detailed I/V
curve, refer to the IBIS models (SAR 34759).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
Added values for minimum pulse width and removed the FRMAX row from Table 2-67
software to determine the FRMAX for the device you are using (SAR 36956).
through
indicating that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
34823).
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-34 FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35743).
Reference was made to a new application note, Simultaneous Read-Write Operations
detail (SAR 34871).
The "Pin Descriptions and Packaging" chapter has been added (SAR 34772).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "ProASIC3
nano Device Status" table on page II indicates the status for each device in the device
family.
N/A
Revision 8
(April 2010)
References to differential inputs were removed from the datasheet, since ProASIC3
nano devices do not support differential inputs (SAR 21449).
N/A
The JTAG DC voltage was revised in Table 2-2 Recommended Operating
Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming voltage
(operation mode) was changed from 3.45 V to 3.6 V (SAR 25220).
Timing Delays was changed to 100C.
The typical value for A3PN010 was revised in Table 2-7 Quiescent Supply Current
Characteristics. The note was revised to remove the statement that values do not
include I/O static contribution.
Revision
Changes
Page
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