2-12 Revision 13 User I/O Characteristics Timing Model Figure 2-2 Timing Model
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PE1500-FG676
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 82/162闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1.5M 676-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷�(j矛)锛� 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 444
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 676-FBGA锛�27x27锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�鐣�(d膩ng)鍓嶇82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�
ProASIC3E DC and Switching Characteristics
2-12
Revision 13
User I/O Characteristics
Timing Model
Figure 2-2 Timing Model
Operating Conditions: 鈥�2 Speed, Commercial Temperature Range (TJ = 70掳C), Worst-Case
VCC = 1.425 V
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.36 ns
tPD = 0.87 ns
tDP = 2.74 ns
tPD = 0.51 ns
tPD = 0.47 ns
tDP = 2.39 ns
tDP = 3.30 ns
tCLKQ = 0.59 ns
tDP = 1.53 ns
tSUD = 0.31 ns
tPY = 0.90 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 0.90 ns
tPD = 0.47 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 1.36 ns
tPY = 0.90 ns
tICLKQ = 0.24 ns
tISUD = 0.26 ns
tPY = 1.22 ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
24AA01T-I/MNY IC EEPROM 1KBIT 400KHZ 8TDFN
ACB40DHAR CONN EDGECARD 80POS R/A .050 DIP
11AA010T-I/MNY IC EEPROM 1KBIT 100KHZ 8TDFN
10336-3210-001 JUNCTION SHELL 36POS DK GRAY
A54SX16P-1TQ144I IC FPGA SX 24K GATES 144-TQFP
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A3PE1500-FG676I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 1.5M 676-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASIC3E 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�
A3PE1500-FG896 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3E Flash Family FPGAs
A3PE1500-FG896ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3E Flash Family FPGAs
A3PE1500-FG896I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3E Flash Family FPGAs
A3PE1500-FG896PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3E Flash Family FPGAs