參數(shù)資料
型號(hào): A1425A-STDCQ132M
元件分類: FPGA
英文描述: FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132
封裝: CERAMIC, QFP-132
文件頁(yè)數(shù): 17/54頁(yè)
文件大?。?/td> 343K
代理商: A1425A-STDCQ132M
RadTolerant FPGAs
1- 20
v3.1
Table 1-13 RT1280A, A1280A Input Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
4.0
4.7
ns
tINYL
Pad-to-Y LOW
3.6
4.3
ns
tINGH
G-to-Y HIGH
6.9
8.1
ns
tINGL
G-to-Y LOW
6.6
7.7
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
6.2
7.3
ns
tIRD2
FO=2 Routing Delay
7.2
8.4
ns
tIRD3
FO=3 Routing Delay
7.7
9.1
ns
tIRD4
FO=4 Routing Delay
8.9
10.5
ns
tIRD8
FO=8 Routing Delay
12.9
15.2
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
13.3
18.2
15.7
21.4
ns
tPWH
Minimum Pulse Width HIGH
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tPWL
Minimum Pulse Width LOW
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may
further reduce delays by 0 to 4ns.
相關(guān)PDF資料
PDF描述
A14100A-STDCQG256B FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256
A14100A-STDCQG256M FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256
A1460A-1PQ160M FPGA, 848 CLBS, 6000 GATES, 125 MHz, PQFP160
A1460A-PQ160M FPGA, 848 CLBS, 6000 GATES, 100 MHz, PQFP160
A1460A-1TQ176M FPGA, 848 CLBS, 6000 GATES, 125 MHz, PQFP176
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1425A-VQ100C 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
A1425A-VQ100I 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
A1425A-VQG100C 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
A1425A-VQG100I 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
A1425LK 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:否 類別:傳感器,轉(zhuǎn)換器 >> 磁性 - 霍爾效應(yīng),數(shù)字式開(kāi)關(guān),線性,羅盤 (IC) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感范圍:20mT ~ 80mT 類型:旋轉(zhuǎn) 電源電壓:4.5 V ~ 5.5 V 電流 - 電源:15mA 電流 - 輸出(最大):- 輸出類型:數(shù)字式,PWM,8.5 位串行 特點(diǎn):可編程 工作溫度:-40°C ~ 150°C 封裝/外殼:20-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:Digi-Reel® 其它名稱:AS5132-HSST-500DKR