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| 型號(hào)： | A14100A-1CQ256B |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256 |
| 封裝： | CERAMIC, CQFP-256 |
| 文件頁數(shù)： | 6/54頁 |
| 文件大?。?/td> | 333K |
| 代理商： | A14100A-1CQ256B |
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RadTolerant FPGAs
1- 10
v3.1
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic
must be known. EQ 1-5 shows a piece-wise linear summation over all components. Since the RT1280A and A1280A
have two routed array clocks, the dedicated_Clk and IO_Clk terms do not apply. For all other devices all terms apply.
Power = VCC
2 * [(m * C
EQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1
*fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk]
EQ 1-5
where:
m
=
Number of logic modules switching at fm
n
=
Number of input buffers switching at fn
p
=
Number of output buffers switching at fp
q1
=
Number of clock loads on the first routed array
clock
q2
=
Number of clock loads on the second routed array
clock (not applicable for RT1020 or A1020B)
r1
=
Fixed capacitance due to first routed array clock
r2
=
Fixed capacitance due to second routed array clock
(not applicable for RT1020 or A1020B)
s1
=
Fixed number of clock loads on the dedicated array
clock
(not
applicable
for
RT1020,
A1020B,
RT1280A, or A1280A)
s2
=
Fixed number of clock loads on the dedicated
I/O clock (not applicable for RT1020, A1020B,
RT1280A, or A1280A)
CEQM =
Equivalent capacitance of logic modules in pF
CEQI
=
Equivalent capacitance of input buffers in pF
CEQO
=
Equivalent capacitance of output buffers in pF
CEQCR =
Equivalent capacitance of routed array clock in pF
CEQCD =
Equivalent capacitance of dedicated array clock
in pF
CEQCI =
Equivalent capacitance of dedicated I/O clock in pF
CL
=
Output lead capacitance in pF
fm
=
Average logic module switching rate in MHz
fn
=
Average input buffer switching rate in MHz
fp
=
Average output buffer switching rate in MHz
fq1
=
Average first routed array clock rate in MHz
fq2
=
Average second routed array clock rate in MHz (not
applicable for RT1020 or A1020B)
fs1
=
Average dedicated array clock rate in MHz (not
applicable for RT1020, A1020B, RT1280A, or
A1280A)
fs2
=
Average dedicated I/O clock rate in MHz
(not applicable for RT1020, A1020B, RT1280A, or
A1280A)
Table 1-8 Fixed Capacitance Values for Actel FPGAs (pF)
Device Type
r1
routed_Clk1
r2
routed_Clk2
RT1020, A1020B
69
n/a
RT1280A, A1280A
168
RT1425A, A1425A
75
RT1460A, A1460A
165
RT14100A, A14100A
195
Table 1-9 Fixed Clock Loads (s1/s2 – ACT 3 Only)
Device Type
s1
Clock Loads
on Dedicated
Array Clock
s2
Clock Loads
on Dedicated
I/O Clock
RT1425A, A1425A
160
100
RT1460A, A1460A
432
168
RT14100A, A14100A
697
228
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A1280A-1CQ172E | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1460A-1CQ196E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CQFP196 |
| A1460A-1PG207E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CPGA207 |
| A1460A-CQ196E | FPGA, 848 CLBS, 6000 GATES, 85 MHz, CQFP196 |
| A1460A-PG207E | FPGA, 848 CLBS, 6000 GATES, 85 MHz, CPGA207 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A14100A-1CQ256BX3 | 制造商:Microsemi Corporation 功能描述:FPGA,ACT3 FAMILY,OTP DEVICE,5V SINGLE LOT DATE CODE - Trays |
| A14100A-1CQ256C | 功能描述:IC FPGA 10K GATES 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A14100A-1CQ256E | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1CQ256M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 125MHz 0.8um Technology 5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL |
| A14100A-1PG256B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
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