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參數(shù)資料
| 型號： | A14100A-1CQ256B |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256 |
| 封裝： | CERAMIC, CQFP-256 |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 333K |
| 代理商： | A14100A-1CQ256B |
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RadTolerant FPGAs
v3.1
1-31
Pin Descriptions
CLK
Clock (Input)
RT1020 and A1020B only. TTL clock input for global clock
distribution networks. The clock input is buffered prior
to clocking the logic modules. This pin can also be used
as an I/O.
CLKA
Clock A (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
CLKB
Clock B (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-Wired) Array Clock
(Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for sequential modules. This
input is directly wired to each S-module, offering clock
speeds independent of the number of S-modules being
driven. This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bidirectional buffer.
Input
and
output
levels
are
compatible with standard TTL and CMOS specifications.
In the RT1020, A1020B, RT1280, and A1280A devices,
unused I/O pins are automatically driven LOW. In the
RT1425,
A1425A,
RT1460,
A1460A,
RT14100,
and
A14100A devices, unused I/O pins are automatically
tristated.
IOCLK
Dedicated (Hard-Wired) I/O Clock (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for I/O modules. This input is
directly wired to each I/O module, offering clock speeds
independent of the number of I/O modules being driven.
This pin can also be used as an I/O.
IOPCL
Dedicated (Hard-Wired) I/O
Preset/Clear (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL input for I/O preset or clear. This global
input is directly wired to the preset and clear inputs of all
I/O registers. This pin functions as an I/O when no I/O
preset or clear macros are used.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the
pins function as I/Os. To provide debugging capability,
the MODE pin should be terminated to GND through a
10 k
Ω resistor so that the MODE pin can be pulled HIGH
when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
A pin to allow real-time diagnostic output of any signal
path within the device. The Probe B pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRB is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
VCC
5.0 V Supply Voltage
HIGH supply voltage.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A1280A-1CQ172E | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1460A-1CQ196E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CQFP196 |
| A1460A-1PG207E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CPGA207 |
| A1460A-CQ196E | FPGA, 848 CLBS, 6000 GATES, 85 MHz, CQFP196 |
| A1460A-PG207E | FPGA, 848 CLBS, 6000 GATES, 85 MHz, CPGA207 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A14100A-1CQ256BX3 | 制造商:Microsemi Corporation 功能描述:FPGA,ACT3 FAMILY,OTP DEVICE,5V SINGLE LOT DATE CODE - Trays |
| A14100A-1CQ256C | 功能描述:IC FPGA 10K GATES 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A14100A-1CQ256E | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1CQ256M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 125MHz 0.8um Technology 5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL |
| A14100A-1PG256B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
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